Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
Algorithms for VLSI Design Automation
Algorithms for VLSI Design Automation
A Fault-Tolerant and Deadlock-Free Routing Protocol in 2D Meshes Based on Odd-Even Turn Model
IEEE Transactions on Computers
A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Proceedings of the 42nd annual Design Automation Conference
Applied Stochastic Models in Business and Industry - Reliability
Analysis of Error Recovery Schemes for Networks on Chips
IEEE Design & Test
Design and analysis of an NoC architecture from performance, reliability and energy perspective
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
Exploring Fault-Tolerant Network-on-Chip Architectures
DSN '06 Proceedings of the International Conference on Dependable Systems and Networks
Proceedings of the 43rd annual Design Automation Conference
Information theoretic approach to address delay and reliability in long on-chip interconnects
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks
Proceedings of the conference on Design, automation and test in Europe
An Analytical Model for Reliability Evaluation of NoC Architectures
IOLTS '07 Proceedings of the 13th IEEE International On-Line Testing Symposium
Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions
Journal of Systems Architecture: the EUROMICRO Journal
Yield and Cost Analysis of a Reliable NoC
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
Vicis: a reliable network for unreliable silicon
Proceedings of the 46th Annual Design Automation Conference
Yield enhancement by robust application-specific mapping on Network-on-Chips
Proceedings of the 2nd International Workshop on Network on Chip Architectures
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Overcoming Early-Life Failure and Aging for Robust Systems
IEEE Design & Test
Shoestring: probabilistic soft error reliability on the cheap
Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems
Compiler directed network-on-chip reliability enhancement for chip multiprocessors
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
A low-overhead and reliable switch architecture for Network-on-Chips
Integration, the VLSI Journal
Computer Networks: The International Journal of Computer and Telecommunications Networking
Models of Network Reliability: Analysis, Combinatorics, and Monte Carlo
Models of Network Reliability: Analysis, Combinatorics, and Monte Carlo
Self-adaptive system for addressing permanent errors in on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Complement routing: A methodology to design reliable routing algorithm for Network on Chips
Microprocessors & Microsystems
A methodology for the characterization of process variation in NoC links
Proceedings of the Conference on Design, Automation and Test in Europe
TIMBER: time borrowing and error relaying for online timing error resilience
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
A method to remove deadlocks in networks-on-chips with wormhole flow control
Proceedings of the Conference on Design, Automation and Test in Europe
A highly resilient routing algorithm for fault-tolerant NoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Coding for system-on-chip networks: a unified framework
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy- and performance-aware mapping for regular NoC architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Error control schemes for on-chip communication links: the energy-reliability tradeoff
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Minimizing power supply noise through harmonic mappings in networks-on-chip
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Unified reliability estimation and management of NoC based chip multiprocessors
Microprocessors & Microsystems
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We formulate the problem of energy consumption and reliability oriented application mapping on regular Network-on-Chip topologies. We propose a novel branch-and-bound based algorithm to solve this problem. Reliability is estimated by an efficient Monte Carlo algorithm based on the destruction spectrum of the network. Simulation results demonstrate that reliability can be improved without sacrificing much of energy consumption.