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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 36th annual ACM/IEEE Design Automation Conference
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Toward achieving energy efficiency in presence of deep submicron noise
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Odd/even bus invert with two-phase transfer for buses with coupling
Proceedings of the 2002 international symposium on Low power electronics and design
Coupling-driven signal encoding scheme for low-power interface design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 2003 international workshop on System-level interconnect prediction
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Journal of Systems Architecture: the EUROMICRO Journal
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NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Analysis of forward error correction methods for nanoscale networks-on-chip
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On hamming product codes with type-II hybrid ARQ for on-chip interconnects
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A bit-stuffing algorithm for crosstalk avoidance in high speed switching
INFOCOM'10 Proceedings of the 29th conference on Information communications
Error resilience of intra-die and inter-die communication with 3D Spidergon STNoC
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ACM Computing Surveys (CSUR)
International Journal of Computer Applications in Technology
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Global buses in deep-submicron (DSM) system-onchip designs consume significant amounts of power, have large propagation delays, and are susceptible to errors due to DSM noise. Coding schemes exist that tackle these problems individually. In this paper, we present a coding framework derived from a communication-theoretic view of a DSM bus to jointly address power, delay, and reliability. In this framework, the data is first passed through a nonlinear source coder that reduces self and coupling transition activity and imposes a constraint on the peak coupling transitions on the bus. Next, a linear error control coder adds redundancy to enable error detection and correction. The framework is employed to efficiently combine existing codes and to derive novel codes that span a wide range of tradeoffs between bus delay, codec latency, power, area, and reliability. Using simulation results in 0.13-µm CMOS technology, we show that coding is a better alternative to repeater insertion for delay reduction as it reduces power dissipation at the same time. For a 10-mm 4-bit bus, we show that a bus employing the proposed codes achieves up to 2.17× speed-up and 33% energy savings over a bus employing Hamming code. For a 10-mm 32-bit bus, we show that 1.7× speed-up and 27% reduction in energy are achievable over an uncoded bus by employing low-swing signaling without any loss in reliability.