Reducing cross-coupling among interconnect wires in deep-submicron datapath design

Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization

ISPD '00 Proceedings of the 2000 international symposium on Physical design

Domino logic synthesis minimizing crosstalk

Proceedings of the 37th Annual Design Automation Conference

A bus delay reduction technique considering crosstalk

DATE '00 Proceedings of the conference on Design, automation and test in Europe

Noise-aware power optimization for on-chip interconnect

ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design

Explicit formulas and efficient algorithm for moment computation of coupled RC trees with lumped and distributed elements

Proceedings of the conference on Design, automation and test in Europe

Modeling crosstalk noise for deep submicron verification tools

Proceedings of the conference on Design, automation and test in Europe

On-chip interconnections: impact of adjacent lines on timing

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

Bus encoding to prevent crosstalk delay

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design

Routing methodology for minimizing 1nterconnect energy dissipation

Proceedings of the 13th ACM Great Lakes symposium on VLSI

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance

ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design

An Analytical Model for Delay and Crosstalk Estimation with Application to Decoupling

ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design

Reduction of coupling effects by optimizing the 3-D configuration of the routing grid

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power

Exploiting Crosstalk to Speed up On-Chip Buses

Proceedings of the conference on Design, automation and test in Europe - Volume 2

Coding for system-on-chip networks: a unified framework

Proceedings of the 41st annual Design Automation Conference

Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Delay and peak power minimization for on-chip buses using temporal redundancy

GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI

Shielding area optimization under the solution of interconnect crosstalk

Journal of Computer Science and Technology

Exploiting on-chip data behavior for delay minimization

Proceedings of the 2007 international workshop on System level interconnect prediction

Selective shielding: a crosstalk-free bus encoding technique

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Variable latency caches for nanoscale processor

Proceedings of the 2007 ACM/IEEE conference on Supercomputing

A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines

Journal of Electronic Testing: Theory and Applications

Selective shielding technique to eliminate crosstalk transitions

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Delay-efficient bus encoding techniques

Microprocessors & Microsystems

Coding for system-on-chip networks: a unified framework

IEEE Transactions on Very Large Scale Integration (VLSI) Systems