Interconnect design for deep submicron ICs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Fault simulation of interconnect opens in digital CMOS circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Reducing cross-coupling among interconnect wires in deep-submicron datapath design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Detectability Conditions of Full Opens in the Interconnections
Journal of Electronic Testing: Theory and Applications
Resistance Characterization for Weak Open Defects
IEEE Design & Test
Residual Charge on the Faulty Floating Gate MOS Transistor
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Defect Classes - An Overdue Paradigm for CMOS IC
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Transient Power Supply Current Testing of Digital CMOS Circuits
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
The Behavior and Testing Implications of CMOS IC Logic Gate Open Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
High volume microprocessor test escapes, an analysis of defects our tests are missing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Proceedings of the IEEE International Test Conference 2001
Test generation for crosstalk-induced faults: framework and computational results
ATS '00 Proceedings of the 9th Asian Test Symposium
An unexpected factor in testing for CMOS opens: the die surface
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Detectability Conditions for Interconnection Open Defects
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Persistent Diagnostic Technique for Unstable Defects
ITC '02 Proceedings of the 2002 IEEE International Test Conference
XIDEN: Crosstalk Target Identification Framework
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Defect-Based Delay Testing of Resistive Vias-Contacts A Critical Evaluation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Estimating detection probability of interconnect opens using stuck-at tests
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Test of Interconnection Opens Considering Coupling Signals
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Interconnect Open Defect Diagnosis with Physical Information
ATS '06 Proceedings of the 15th Asian Test Symposium
Diagnosis of Full Open Defects in Interconnecting Lines
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines
DFT '07 Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
ATS '07 Proceedings of the 16th Asian Test Symposium
Oscillation and sequential behavior caused by opens in the routing in digital CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Voltage- and current-based fault simulation for interconnect open defects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Experimental Characterization of CMOS Interconnect Open Defects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Interconnection opens have become important defects in nanometer technologies. The behavior of these defects depends on the structure of the affected devices, the trapped gate charge and the surrounding circuitry. This work proposes an enhanced test generation methodology to improve the detectability of interconnection opens. This test methodology is called OPVEG. OPVEG uses layout information and a commercial stuck-at ATPG. Those signal values at the coupled lines which favor the detection of the opens, under a boolean based test, are attempted to be generated. The methodology is applied to four ISCAS85 benchmark circuits. The results show that a significant number of considered coupled signals are set to proper logic values. Hence, the likelihood of detection of interconnection opens is increased. The results are also given in terms of the amount of coupling capacitance having logic conditions favoring the defect detection. This shows the OPVEG benefits. Furthermore, those lines difficult to test can be identified. This information can be used by the designer to take design for test measures.