The Behavior and Testing Implications of CMOS IC Logic Gate Open Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Bridging Defects Resistance Measurements in a CMOS Process
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
High volume microprocessor test escapes, an analysis of defects our tests are missing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Testability of floating gate defects in sequential circuits
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Defect-Based Delay Testing of Resistive Vias-Contacts A Critical Evaluation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours
Journal of Electronic Testing: Theory and Applications
New Test Methodology for Resistive Open Defect Detection in Memory Address Decoders
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
A Statistical Fault Coverage Metric for Realistic Path Delay Faults
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test
Journal of Electronic Testing: Theory and Applications
On test conditions for the detection of open defects
Proceedings of the conference on Design, automation and test in Europe: Proceedings
ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions
Journal of Electronic Testing: Theory and Applications
Test quality analysis and improvement for an embedded asynchronous FIFO
Proceedings of the conference on Design, automation and test in Europe
Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits
Journal of Electronic Testing: Theory and Applications
A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines
Journal of Electronic Testing: Theory and Applications
Using test data to improve IC quality and yield
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Ramp Voltage Testing for Detecting Interconnect Open Faults
IEICE - Transactions on Information and Systems
Delay caused by resistive opens in interconnecting lines
Integration, the VLSI Journal
Testing resistive opens and bridging faults through pulse propagation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An analytical model for soft error critical charge of nanometric SRAMs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical path selection for at-speed test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multi-temperature testing for core-based system-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Study of Read Recovery Dynamic Faults in 6T SRAMS and Method to Improve Test Time
Journal of Electronic Testing: Theory and Applications
Delay sensing for long-term variations and defects monitoring in safety---critical applications
Analog Integrated Circuits and Signal Processing
Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes
Journal of Electronic Testing: Theory and Applications
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Strong open defects can cause a circuit tomalfunction, but even weak open defects cancause it to function poorly. Detecting weak opensis thus an important, but challenging, task.Characterizing weak opens can help researchersassess the need for delay fault tests.