Resistance Characterization for Weak Open Defects
IEEE Design & Test
A Systematic DFT Procedure for Library Cells
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Test Strategy Sensitivity to Defect Parameters
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Optimal Conditions for Boolean and Current Detection of Floating Gate Faults
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An Effective and Accurate Methodology for the Cell Internal Defect Diagnosis
Journal of Electronic Testing: Theory and Applications
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Abstract: The logic detectability conditions of floating gate (FG) defects in sequential circuits are considered. It has been found that a FG defective sequential circuit may be able to memorize one or two logic states depending on the values of the defect parameters. I/sub DDQ/ testing may detect a large class of floating gate defects including some defective transistors located in logically untestable branches. Good agreement is observed between the theoretical and simulated results with experimental measurements performed on a typical scan path cell designed intentionally with floating gate defects.