Analysis of the Floating Gate Defect in CMOS
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
The Behavior and Testing Implications of CMOS IC Logic Gate Open Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Test Strategy Sensitivity to Defect Parameters
Proceedings of the IEEE International Test Conference
Testing for Floating Gates Defects in CMOS Circuits
ATS '98 Proceedings of the 7th Asian Test Symposium
An unexpected factor in testing for CMOS opens: the die surface
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Testability of floating gate defects in sequential circuits
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Defect classes - an overdue paradigm for CMOS IC testing
ITC'94 Proceedings of the 1994 international conference on Test
Residual charge on the faulty floating gate MOS transistor
ITC'94 Proceedings of the 1994 international conference on Test
Electrical model of the floating gate defect in CMOS ICs: implications on IDDQ testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Detectability Conditions of Full Opens in the Interconnections
Journal of Electronic Testing: Theory and Applications
Digital Signature Proposal for Mixed-Signal Circuits
Journal of Electronic Testing: Theory and Applications
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Digital Signature Proposal for Mixed-Signal Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Ramp Voltage Testing for Detecting Interconnect Open Faults
IEICE - Transactions on Information and Systems
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This paper studies the Boolean (Static Voltage) and theIddq (Static Current) detection of Floating Gate faults due to largeopens on transistor gate connections. We show that existingelectrical models describing the behavior of FGT faults fail toallow the prediction of the floating gate potential due to theunpredictable parameters such as the initial charges and thepolysilicon-to-bulk capacitance. We propose the twin-transistorstructure as a basis for a general analysis of the Boolean and Iddqdetection of FGT faults. Using this analysis, optimal conditions fordetection are defined for Boolean as well as Iddq tests.