Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Resistance Characterization for Weak Open Defects
IEEE Design & Test
Testing for resistive opens and stuck opens
Proceedings of the IEEE International Test Conference 2001
Multiple-output propagation transition fault test
Proceedings of the IEEE International Test Conference 2001
Comparison of Defect Detection Capabilities of Current-Based and Voltage-Based Test Methods
ETW '00 Proceedings of the IEEE European Test Workshop
Comparison of Defect Detection Capabilities of Current-Based and Voltage-Based Test Methods
ETW '00 Proceedings of the IEEE European Test Workshop
Detectability Conditions for Interconnection Open Defects
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
A Circuit Level Fault Model for Resistive Opens and Bridges
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Parametric Failures in CMOS ICs " A Defect-Based Analysis
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Optimal Conditions for Boolean and Current Detection of Floating Gate Faults
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Estimating detection probability of interconnect opens using stuck-at tests
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Engineering Circuit Analysis
XID: Don't care identification of test patterns for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A method for detecting interconnect open faults of CMOS combinational circuits by applying a ramp voltage to the power supply terminal is proposed. The method can assign a known logic value to a fault location automatically by applying a ramp voltage and as a result, it requires only one test vector to detect a fault as a delay fault or an erroneous logic value at primary outputs. In this paper, we show fault detectability and effectiveness of the proposed method by simulation-based and theoretical analysis. We also expose that the method can be applicable to every fault location in a circuit and open faults with any value. Finally, we show ATPG results that are suitable to the proposed method.