A new 4-2 adder and booth selector for low power MAC unit
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Datapath scheduling with multiple supply voltages and level converters
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Logic synthesis for large pass transistor circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Minimization of chip size and power consumption of high-speed VLSI buffers
Proceedings of the 1997 international symposium on Physical design
Design and optimization of low voltage high performance dual threshold CMOS circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Figures of merit to characterize the importance of on-chip inductance
DAC '98 Proceedings of the 35th annual Design Automation Conference
Low-swing interconnect interface circuits
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Low power architecture of the soft-output Viterbi algorithm
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Energy-efficiency in presence of deep submicron noise
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Configuration cloning: exploiting regularity in dynamic DSP architectures
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Interconnect coupling noise in CMOS VLSI circuits
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Analog versus digital: extrapolating from electronics to neurobiology
Neural Computation
High speed GaAs subsytem design using feed through logic
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Wave steering in YADDs: a novel non-iterative synthesis and layout technique
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Equivalent Elmore delay for RLC trees
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Lowering power consumption in clock by using globally asynchronous locally synchronous design style
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Energy-efficient signal processing via algorithmic noise-tolerance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Ultra-low power digital subthreshold logic circuits
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Low power synthesis of dual threshold voltage CMOS VLSI circuits
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
High-performance bidirectional repeaters
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Digital CMOS logic operation in the sub-threshold region
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
A comparative study of power efficient SRAM designs
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Buffer minimization in pass transistor logic
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Optimal reliable crosstalk-driven interconnect optimization
ISPD '00 Proceedings of the 2000 international symposium on Physical design
A design of and design tools for a novel quantum dot based microprocessor
Proceedings of the 37th Annual Design Automation Conference
Optimum loading dispersion for high-speed tree-type decision circuitry
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Efficient resource arbitration in reconfigurable computing environments
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Design and Implementation of the MorphoSys Reconfigurable ComputingProcessor
Journal of VLSI Signal Processing Systems - Special issue on VLSI on custom computing technology
MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
SensorSim: a simulation framework for sensor networks
Proceedings of the 3rd ACM international workshop on Modeling, analysis and simulation of wireless and mobile systems
A static power model for architects
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
A Low Power 8 × 8 Direct 2-D DCT Chip Design
Journal of VLSI Signal Processing Systems
A static power estimation methodolodgy for IP-based design
Proceedings of the conference on Design, automation and test in Europe
A VLSI wrapped wave front arbiter for crossbar switches
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
An efficient analytical model of coupled on-chip RLC interconnects
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Cell selection from technology libraries for minimizing power
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
High-level synthesis under multi-cycle interconnect delay
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
JouleTrack: a web based tool for software energy profiling
Proceedings of the 38th annual Design Automation Conference
Built-in self-test for signal integrity
Proceedings of the 38th annual Design Automation Conference
Theory and practical implementation of harmonic resonant rail driver
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Ultra-low power DLMS adaptive filter for hearing aid applications
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Analysis and implementation of charge recycling for deep sub-micron buses
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Circuit design of routing switches
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Power estimation in adiabatic circuits: a simple and accurate model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Soft digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Signal integrity fault analysis using reduced-order modeling
Proceedings of the 39th annual Design Automation Conference
DRG-cache: a data retention gated-ground cache for low power
Proceedings of the 39th annual Design Automation Conference
Logic transformation for low-power synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power and performance evaluation of globally asynchronous locally synchronous processors
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Energy recovering static memory
Proceedings of the 2002 international symposium on Low power electronics and design
High performance and low power FIR filter design based on sharing multiplication
Proceedings of the 2002 international symposium on Low power electronics and design
Parametric timing and power macromodels for high level simulation of low-swing interconnects
Proceedings of the 2002 international symposium on Low power electronics and design
Automated design synthesis and partitioning for adaptive reconfigurable hardware
Hardware implementation of intelligent systems
PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Minimum-power retiming for dual-supply CMOS circuits
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Mixed-Technology System-Level Simulation
Analog Integrated Circuits and Signal Processing
Behavioral Model of Analog Circuits for Nonvolatile Memories with VHDL-AMS
Analog Integrated Circuits and Signal Processing
The Flagged Prefix Adder and its Applications in Integer Arithmetic
Journal of VLSI Signal Processing Systems
Synthesis of CMOS domino circuits for charge sharing alleviation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Frequency domain analysis of switching noise on power supply network
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
CASh: a novel "clock as shield" design methodology for noise immune precharge-evaluate logic
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
O2 ABA: a novel high-performance predictable circuit architecture for the deep submicron era
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A bus energy model for deep submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Signal Integrity: Fault Modeling and Testing in High-Speed SoCs
Journal of Electronic Testing: Theory and Applications
An FPGA architecture with enhanced datapath functionality
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Long and Fast Up/Down Counters
IEEE Transactions on Computers
Scalable hybrid computation with spikes
Neural Computation
Leakage Energy Management in Cache Hierarchies
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
High Performance and Energy Efficient Serial Prefetch Architecture
ISHPC '02 Proceedings of the 4th International Symposium on High Performance Computing
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Impact of Voltage Scaling on Glitch Power Consumption
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
An FPGA Implementation of the Linear Cryptanalysis
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Embedded Reconfigurable Logic Core for DSP Applications
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
High-Speed RSA Hardware Based on Barret's Modular Reduction Method
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
Optical Fault Induction Attacks
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Techniques for Estimation of Design Diversity for Combinational Logic Circuits
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
Iterative decoding in analog CMOS
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Design issues in low-voltage high-speed current-mode logic buffers
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Buffer sizing for minimum energy-delay product by using an approximating polynomial
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Efficient Uses of FPGAs for Implementations of DES and Its Experimental Linear Cryptanalysis
IEEE Transactions on Computers
Interconnect-aware high-level synthesis for low power
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Optimal buffered routing path constructions for single and multiple clock domain systems
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A survey of techniques for energy efficient on-chip communication
Proceedings of the 40th annual Design Automation Conference
Wave steering to integrate logic and physical syntheses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Power aware computing
Asynchronous DRAM Design and Synthesis
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
FRONTIERS '96 Proceedings of the 6th Symposium on the Frontiers of Massively Parallel Computation
Associative Matrix for Nano-Scale Integrated Circuits
MICRONEURO '99 Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems
Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Switch-level Delay Test of Domino Logic Circuits
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Testing Interconnects for Noise and Skew in Gigahertz SoCs
ITC '01 Proceedings of the 2001 IEEE International Test Conference
AN IDDQ SENSOR CIRCUIT FOR LOW-VOLTAGE ICS
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Analysis and Optimization of Ground Bounce in Digital CMOS Circuits
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
A Graph Theoretic Approach for Design and Synthesis of Multiplierless FIR Filters
Proceedings of the 12th international symposium on System synthesis
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
An ASIC design methodology with predictably low leakage, using leakage-immune standard cells
Proceedings of the 2003 international symposium on Low power electronics and design
IDDT: fundamentals and test generation
Journal of Computer Science and Technology
Critical Path Identification and Delay Tests of Dynamic Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Ground bounce in digital VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A true single-phase energy-recovery multiplier
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Maximizing throughput over parallel wire structures in the deep submicrometer regime
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-performance FIR filter design based on sharing multiplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CMOS VLSI Implementation of a Low-Power Logarithmic Converter
IEEE Transactions on Computers
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
A clock-tuning circuit for system-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Voltage-pulse driven harmonic resonant rail drivers for low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Reduced energy decoding of MPEG streams
Multimedia Systems
Performance evaluation of the low-voltage CML D-latch topology
Integration, the VLSI Journal - Special issue on analog and mixed-signal IC design and design methodologies
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Analog Integrated Circuits and Signal Processing
Opportunities and challenges in application-tuned circuits and architectures based on nanodevices
Proceedings of the 1st conference on Computing frontiers
Timing modeling and optimization under the transmission line model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Circuit and microarchitectural techniques for reducing cache leakage power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling of transmission lines with EM wave coupling by the finite difference quadrature method
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Design and optimization of MOS current mode logic for parameter variations
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Low energy FPGA interconnect design
Proceedings of the 14th ACM Great Lakes symposium on VLSI
The best of both worlds: the efficient asynchronous implementation of synchronous specifications
Proceedings of the 41st annual Design Automation Conference
Theoretical and practical limits of dynamic voltage scaling
Proceedings of the 41st annual Design Automation Conference
A CAD-Based Investigation of Clock-Skew Hazards in Pipelined NORA Dynamic Logic Circuits
Analog Integrated Circuits and Signal Processing
Exploiting Resonant Behavior to Reduce Inductive Noise
Proceedings of the 31st annual international symposium on Computer architecture
Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware Threading
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Binding, Allocation and Floorplanning in Low Power High-Level Synthesis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A High-level Interconnect Power Model for Design Space Exploration
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2004 international symposium on Low power electronics and design
A thread partitioning algorithm in low power high-level synthesis
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Optimal design of high fan-in multiplexers via mixed-integer nonlinear programming
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Gate delay calculation considering the crosstalk capacitances
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Alloyed branch history: combining global and local branch history for robust performance
International Journal of Parallel Programming
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Transistor-Level Static Timing Analysis by Piecewise Quadratic Waveform Matching
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Efficient Design Diversity Estimation for Combinational Circuits
IEEE Transactions on Computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power on-chip communication based on transition-aware global signaling (TAGS)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-performance and low-power conditional discharge flip-flop
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reliable low-power digital signal processing via reduced precision redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low-power reduced swing global clocking methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy management schemes for memory-resident database systems
Proceedings of the thirteenth ACM international conference on Information and knowledge management
Quadrature direct digital frequency synthesizers using interpolation-based angle rotation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Enhancing Yield at the End of the Technology Roadmap
IEEE Design & Test
Critical evaluation of SOI design guidelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
RL-huffman encoding for test compression and power reduction in scan applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design of ultrahigh-speed low-voltage CMOS CML buffers and latches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Evaluation of energy consumption in RC ladder circuits driven by a ramp input
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
On Statistical Timing Analysis with Inter- and Intra-Die Variations
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Smart Temperature Sensor for Thermal Testing of Cell-Based ICs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Design Method for Constant Power Consumption of Differential Logic Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Simultaneous Reduction of Dynamic and Static Power in Scan Structures
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Stochastic Power Grid Analysis Considering Process Variations
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip
Journal of VLSI Signal Processing Systems
Quantifying Error in Dynamic Power Estimation of CMOS Circuits
Analog Integrated Circuits and Signal Processing
Fault tolerant bus architecture for deep submicron based processors
ACM SIGARCH Computer Architecture News - Special issue: Workshop on architectural support for security and anti-virus (WASSA)
Self-timed communication platform for implementing high-performance systems-on-chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Multi-GHz SiGe design methodologies for reconfigurable computing
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
An analysis of the robustness of CMOS delay elements
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
A detailed power model for field-programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A robust self-calibrating transmission scheme for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Partitioning and placement for buildable QCA circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A New CMOS Current-Mode Multiplexer for l0 Gbps Serial Links
Analog Integrated Circuits and Signal Processing
Instantaneous current modeling in a complex VLIW processor core
ACM Transactions on Embedded Computing Systems (TECS)
Cascaded carry-select adder (C2SA): a new structure for low-power CSA design
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Power-aware code scheduling for clusters of active disks
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Self-timed circuits for energy harvesting AC power supplies
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Soft-Spot Analysis: Targeting Compound Noise Effects in Nanometer Circuits
IEEE Design & Test
Power-smart system-on-chip architecture for embedded cryptosystems
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Power optimization for universal hash function data path using divide-and-concatenate technique
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Energy management for commodity short-bit-width microcontrollers
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Exploring the limits of leakage power reduction in caches
ACM Transactions on Architecture and Code Optimization (TACO)
Ripple-Precharge TCAM A Low-Power Solution for Network Search Engines
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Minimum Energy Near-threshold Network of PLA based Design
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Hardware/software managed scratchpad memory for embedded system
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A metal and via maskset programmable VLSI design methodology using PLAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A novel clock distribution and dynamic de-skewing methodology
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A 90nm low-power FPGA for battery-powered applications
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
A reconfigurable architecture for hybrid CMOS/Nanodevice circuits
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture
Proceedings of the 2006 international workshop on System-level interconnect prediction
Physical design implementation of segmented buses to reduce communication energy
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Technology mapping for low leakage power and high speed with hot-carrier effect consideration
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Power minimization for dynamic PLAs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Opportunities and challenges for better than worst-case design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A novel data processing circuit in high-speed serial communication
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Reliable crosstalk-driven interconnect optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SRAM Local Bit Line Access Failure Analyses
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Analysis of Process Variation's Effect on SRAM's Read Stability
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Design approaches for hybrid CMOS/molecular memory based on experimental device data
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Double-gate SOI devices for low-power and high-performance applications
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Post-verification debugging of hierarchical designs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Journal of VLSI Signal Processing Systems
Crosstalk Induced Fault Analysis and Test in DRAMs
Journal of Electronic Testing: Theory and Applications
Procrastination for leakage-aware rate-monotonic scheduling on a dynamic voltage scaling processor
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
Origins and motivations for design rules in QCA
Nano, quantum and molecular computing
Partitioning and placement for buildable QCA circuits
Nano, quantum and molecular computing
A PLA based asynchronous micropipelining approach for subthreshold circuit design
Proceedings of the 43rd annual Design Automation Conference
Circuits for energy harvesting sensor signal processing
Proceedings of the 43rd annual Design Automation Conference
MARS-C: modeling and reduction of soft errors in combinational circuits
Proceedings of the 43rd annual Design Automation Conference
Reconfigurable Coprocessor for Multimedia Application Domain
Journal of VLSI Signal Processing Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and implementation of a high-speed matrix multiplier based on word-width decomposition
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The limit of dynamic voltage scaling and insomniac dynamic voltage scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A cell library for low power high performance CMOS voltage-mode quaternary logic
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Integration, the VLSI Journal
Energy-efficient motion estimation using error-tolerance
Proceedings of the 2006 international symposium on Low power electronics and design
High-performance CMOS variability in the 65-nm regime and beyond
IBM Journal of Research and Development - Advanced silicon technology
Ultra low-cost defect protection for microprocessor pipelines
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
SHAPES:: a tiled scalable software hardware architecture platform for embedded systems
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Post-route LUT output polarity selection for timing optimization
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Mixed Full Adder topologies for high-performance low-power arithmetic circuits
Microelectronics Journal
Multiplier-less VLSI architecture for real-time computation of multi-dimensional convolution
Microprocessors & Microsystems
A two-level reconfigurable architecture for digital signal processing
Microelectronic Engineering
Fast hardware for modular exponentiation with efficient exponent pre-processing
Journal of Systems Architecture: the EUROMICRO Journal
Structured and tuned array generation (STAG) for high-performance random logic
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Designing CMOS/molecular memories while considering device parameter variations
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Impact of interconnect length changes on effective materials properties (dielectric constant)
Proceedings of the 2007 international workshop on System level interconnect prediction
Power and electromagnetic analysis: improved model, consequences and comparisons
Integration, the VLSI Journal - Special issue: Embedded cryptographic hardware
Design of efficient architectures for 1-D and 2-D DLMS adaptive filters
Integration, the VLSI Journal
Online task-scheduling for fault-tolerant low-energy real-time systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load
Integration, the VLSI Journal
A Low-Latency and Low-Power Hybrid Insertion Methodology for Global Interconnects in VDSM Designs
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Energy-efficient Hardware Accelerators for the SA-DCT and Its Inverse
Journal of VLSI Signal Processing Systems
High performance low power CMOS dynamic logic for arithmetic circuits
Microelectronics Journal
An analysis of interconnect delay minimization by low-voltage repeater insertion
Microelectronics Journal
Proceedings of the conference on Design, automation and test in Europe
Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits
Proceedings of the conference on Design, automation and test in Europe
Rapid and accurate latch characterization via direct Newton solution of setup/hold times
Proceedings of the conference on Design, automation and test in Europe
Thermally robust clocking schemes for 3D integrated circuits
Proceedings of the conference on Design, automation and test in Europe
Energy-efficient real-time task scheduling with task rejection
Proceedings of the conference on Design, automation and test in Europe
A proposal to introduce power and energy notions in computer architecture laboratories
WCAE '07 Proceedings of the 2007 workshop on Computer architecture education
Proceedings of the 44th annual Design Automation Conference
Towards an ultra-low-power architecture using single-electron tunneling transistors
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 44th annual Design Automation Conference
Variation resilient low-power circuit design methodology using on-chip phase locked loop
Proceedings of the 44th annual Design Automation Conference
Lightweight floating-point arithmetic: case study of inverse discrete cosine transform
EURASIP Journal on Applied Signal Processing
Low-power process-variation tolerant arithmetic units using input-based elastic clocking
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Functionally Fault-tolerant DSP Microprocessor using Sigma---delta Modulated Signals
Journal of Electronic Testing: Theory and Applications
High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems
Journal of VLSI Signal Processing Systems
A predictably low-leakage ASIC design style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power clock branch sharing double-edge triggered flip-flop
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Testable designs of multiple precharged domino circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
CMOL: Second life for silicon?
Microelectronics Journal
Area and delay trade-offs in the circuit and architecture design of FPGAs
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Global interconnections in FPGAs: modeling and performance analysis
Proceedings of the 2008 international workshop on System level interconnect prediction
Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger
Journal of Electronic Testing: Theory and Applications
Defect Analysis and Defect Tolerant Design of Multi-port SRAMs
Journal of Electronic Testing: Theory and Applications
A high speed, low voltage to high voltage level shifter in standard 1.2 V 0.13 μm CMOS
Analog Integrated Circuits and Signal Processing
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Towards Ultra-High Resolution Models of Climate and Weather
International Journal of High Performance Computing Applications
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A robust, fast pulsed flip-flop design
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Pipelined network of PLA based circuit design
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A lithography-friendly structured ASIC design approach
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Effecting power consumption reduction in digital CMOS circuits by a hybrid logic synthesis technique
ESPOCO'05 Proceedings of the 4th WSEAS International Conference on Electronic, Signal Processing and Control
Partitioning parameterized 45-degree polygons with constraint programming
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Addressing thermal nonuniformity in SMT workloads
ACM Transactions on Architecture and Code Optimization (TACO)
Versatile multiplier architectures in GF(2k) fields using the Montgomery multiplication algorithm
Integration, the VLSI Journal
AMOLED pixel driver circuits based on poly-Si TFTs: A comparison
Integration, the VLSI Journal
A low-power transmission-gate-based 16-bit multiplier for digital hearing aids
Analog Integrated Circuits and Signal Processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Signal Processing Systems
Trading off Cache Capacity for Reliability to Enable Low Voltage Operation
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
An integrated nonlinear placement framework with congestion and porosity aware buffer planning
Proceedings of the 45th annual Design Automation Conference
Enhancing beneficial jitter using phase-shifted clock distribution
Proceedings of the 13th international symposium on Low power electronics and design
Proceedings of the 13th international symposium on Low power electronics and design
SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip Networks
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
A delay-efficient radiation-hard digital design approach using CWSP elements
Proceedings of the conference on Design, automation and test in Europe
A novel low overhead fault tolerant Kogge-Stone adder using adaptive clocking
Proceedings of the conference on Design, automation and test in Europe
Bandwidth-centric optimisation for area-constrained links with crosstalk avoidance methods
Proceedings of the conference on Design, automation and test in Europe
Power balanced gates insensitive to routing capacitance mismatch
Proceedings of the conference on Design, automation and test in Europe
Variation tolerant NoC design by means of self-calibrating links
Proceedings of the conference on Design, automation and test in Europe
J-map for quantum dot cellular automata
AEE'08 Proceedings of the 7th WSEAS International Conference on Application of Electrical Engineering
Controllability of Static CMOS Circuits for Timing Characterization
Journal of Electronic Testing: Theory and Applications
MINO'08 Proceedings of the 7th WSEAS International Conference on Microelectronics, Nanoelectronics, Optoelectronics
Multiple sleep mode leakage control for cache peripheral circuits in embedded processors
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
A Low Complexity Reconfigurable DCT Architecture to Trade off Image Quality for Power Consumption
Journal of Signal Processing Systems
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
Variability driven gate sizing for binning yield optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Crosstalk analysis for a CMOS gate driven inductively and capacitively coupled interconnects
Microelectronics Journal
Two new low-power Full Adders based on majority-not gates
Microelectronics Journal
Embedded DSP Processor Design: Application Specific Instruction Set Processors
Embedded DSP Processor Design: Application Specific Instruction Set Processors
A shift-register-based QCA memory architecture
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Improved throughput bit-serial multiplier for GF(2m) fields
Integration, the VLSI Journal
System-level PVT variation-aware power exploration of on-chip communication architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
J-map for quantum dot cellular automata
ISCGAV'08 Proceedings of the 8th conference on Signal processing, computational geometry and artificial vision
Closed-loop modeling of power and temperature profiles of FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs)
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
On stress aware active area sizing, gate sizing, and repeater insertion
Proceedings of the 2009 international symposium on Physical design
Dynamically de-skewable clock distribution methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Error-resilient motion estimation architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
EVAL: Utilizing processors with variation-induced timing errors
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Ramp Voltage Testing for Detecting Interconnect Open Faults
IEICE - Transactions on Information and Systems
An interconnect-aware delay model for dynamic voltage scaling in NM technologies
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Better than optimum?: register reduction using idle pipelined functional units
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Proceedings of the 19th ACM Great Lakes symposium on VLSI
New performance/power/area efficient, reliable full adder design
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Secure Hardware Implementation of Non-linear Functions in the Presence of Glitches
Information Security and Cryptology --- ICISC 2008
The impact of speculative execution on SMT processors
International Journal of Parallel Programming
Tolerating process variations in large, set-associative caches: The buddy cache
ACM Transactions on Architecture and Code Optimization (TACO)
Minimizing CPU energy in real-time systems with discrete speed management
ACM Transactions on Embedded Computing Systems (TECS)
Impact of supply voltage variations on full adder delay: analysis and comparison
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Toward the optimal configuration of dynamic voltage scaling points in real-time applications
Journal of Computer Science and Technology
Design space exploration for 3-D cache
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy/area/delay tradeoffs in the physical design of on-chip segmented bus architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analog Integrated Circuits and Signal Processing
Analog Integrated Circuits and Signal Processing
Low-power interface circuits between adiabatic and standard CMOS circuits
Analog Integrated Circuits and Signal Processing
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
A study of asynchronous design methodology for robust CMOS-nano hybrid system design
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder
IWANN '03 Proceedings of the 7th International Work-Conference on Artificial and Natural Neural Networks: Part II: Artificial Neural Nets Problem Solving Methods
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
MicroFix: exploiting path-grained timing adaptability for improving power-performance efficiency
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Journal of Signal Processing Systems
A defect/error-tolerant nanosystem architecture for DSP
ACM Journal on Emerging Technologies in Computing Systems (JETC)
SRAM parametric failure analysis
Proceedings of the 46th Annual Design Automation Conference
Decreasing energy consumption in address decoders by means of selective precharge schemes
Microelectronics Journal
Parallel links with current-mode incremental signaling and per-pin skew compensation
Microelectronics Journal
Design and analysis of UHF micropower CMOS DTMOST rectifiers
IEEE Transactions on Circuits and Systems II: Express Briefs
Designing high-speed adders in power-constrained environments
IEEE Transactions on Circuits and Systems II: Express Briefs
Modified model for settling behavior of operational amplifiers in nanoscale CMOS
IEEE Transactions on Circuits and Systems II: Express Briefs
Power-efficient clock/data distribution technique for polyphase comb filter in digital receivers
IEEE Transactions on Circuits and Systems II: Express Briefs
A low-complexity hybrid LDPC code encoder for IEEE 802.3an (10GBase-T) ethernet
IEEE Transactions on Signal Processing
An improved soft-error rate measurement technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A formal approach for debugging arithmetic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A 9-Gbit/s serial transceiver for on-chip global signaling over lossy transmission lines
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2008 custom integrated circuits conference (CICC 2008)
Design of thermally robust clock trees using dynamically adaptive clock buffers
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Binary morphology with spatially variant structuring elements: algorithm and architecture
IEEE Transactions on Image Processing
Reducing leakage power with BTB access prediction
Integration, the VLSI Journal
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Energy reduction for STT-RAM using early write termination
Proceedings of the 2009 International Conference on Computer-Aided Design
DSP'09 Proceedings of the 16th international conference on Digital Signal Processing
Total Power Optimization for Combinational Logic Using Genetic Algorithms
Journal of Signal Processing Systems
Variable input delay CMOS logic for low power design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and analysis of two low-power SRAM cell structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power clocked-pseudo-NMOS flip-flop for level conversion in dual supply systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A 32-Gb/s on-chip bus with driver pre-emphasis signaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A flexible DSP architecture for MIMO sphere decoding
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Soft NMR: exploiting statistics for energy-efficiency
SOC'09 Proceedings of the 11th international conference on System-on-chip
A low-power content-addressable memory (CAM) using pipelined search scheme
Proceedings of the International Conference and Workshop on Emerging Trends in Technology
An analytical approach to dynamic crosstalk in coupled interconnects
Microelectronics Journal
Wave-pipelined intra-chip signaling for on-FPGA communications
Integration, the VLSI Journal
VECPAR'02 Proceedings of the 5th international conference on High performance computing for computational science
A logic programming framework for combinational circuit synthesis
ICLP'07 Proceedings of the 23rd international conference on Logic programming
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Performance enhancement of subthreshold circuits using substrate biasing and charge-boosting buffers
Proceedings of the 20th symposium on Great lakes symposium on VLSI
SHIELDSTRAP: making secure processors truly secure
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
On improving the algorithmic robustness of a low-power FIR filter
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Enabling power-efficient DVFS operations on silicon
IEEE Circuits and Systems Magazine
Design and analysis of ultra low power true single phase clock CMOS 2/3 prescaler
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Statistical design of the 6T SRAM bit cell
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A power-efficient multipin ILP-based routing technique
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Full 360° vector-sum phase-shifter for microwave system applications
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Design of asynchronous circuits for high soft error tolerance in deep submicrometer CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cost-driven 3D integration with interconnect layers
Proceedings of the 47th Design Automation Conference
RDE-based transistor-level gate simulation for statistical static timing analysis
Proceedings of the 47th Design Automation Conference
Analog circuit shielding routing algorithm based on net classification
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Design and analysis of low powered DNA sequence alignment accelerator using ASIC design flow
MINO'10 Proceedings of the 9th WSEAS international conference on Microelectronics, nanoelectronics, optoelectronics
A GALS pipeline DES architecture to increase robustness against DPA and DEMA attacks
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power consumption of analog circuits: a tutorial
Analog Integrated Circuits and Signal Processing
Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
PPAM'09 Proceedings of the 8th international conference on Parallel processing and applied mathematics: Part I
Technology mapping with crosstalk noise avoidance
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Journal of Parallel and Distributed Computing
Design research of the DES against power analysis attacks based on FPGA
Microprocessors & Microsystems
Variable-latency adder (VL-adder) designs for low power and NBTI tolerance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design margin exploration of spin-transfer torque RAM (STT-RAM) in scaled technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploring area and delay tradeoffs in FPGAs with architecture and automated transistor design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance analysis of FPGA interconnect fabric for ultra-low power applications
Proceedings of the 2011 International Conference on Communication, Computing & Security
Performance optimization of CNFET for ultra-low power reconfigurable architecture
Proceedings of the 2011 International Conference on Communication, Computing & Security
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Power minimization for dynamic PLAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Extraction error modeling and automated model debugging in high-performance custom designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-leakage storage cells for ternary content addressable memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Differential current-sensing for on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
VISION: a framework for voltage island aware synthesis of interconnection networks-on-chip
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Instruction level and operating system profiling for energy exposed software
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Ultra-low-power DLMS adaptive filter for hearing aid applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reliability analysis and optimization of power-gated ICs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improving line-based QCA memory cell design through dual phase clocking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Ultra low-power clocking scheme using energy recovery and clock gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and modeling of energy consumption in RLC tree circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CMOS driver-receiver pair for low-swing signaling for low energy on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Evolving spiking networks with variable memristors
Proceedings of the 13th annual conference on Genetic and evolutionary computation
Clock buffer polarity assignment with skew tuning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systems
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
IMPACT: imprecise adders for low-power approximate computing
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Evolving spiking networks with variable memristors
ACM SIGEVOlution
Segmented bitline cache: exploiting non-uniform memory access patterns
HiPC'06 Proceedings of the 13th international conference on High Performance Computing
Power-aware virtual machine scheduling on clouds using active cooling control and DVFS
Proceedings of the 9th International Workshop on Middleware for Grids, Clouds and e-Science
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
On the complexity of min-max sorting networks
Information Sciences: an International Journal
Side-channel leakage of masked CMOS gates
CT-RSA'05 Proceedings of the 2005 international conference on Topics in Cryptology
Output resistance scaling model for deep-submicron cmos buffers for timing performance optimisation
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Power – performance optimization for custom digital circuits
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Design of variable input delay gates for low dynamic power circuits
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Fast low-power 64-bit modular hybrid adder
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Successfully attacking masked AES hardware implementations
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Masked dual-rail pre-charge logic: DPA-resistance without routing constraints
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Masking at gate level in the presence of glitches
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Improved higher-order side-channel attacks with FPGA experiments
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Power modeling of precharged address bus and application to multi-bit DPA attacks to DES algorithm
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Techniques to enhance the resistance of precharged busses to differential power analysis
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Impact of rotations in SHA-1 and related hash functions
SAC'05 Proceedings of the 12th international conference on Selected Areas in Cryptography
Integration, the VLSI Journal
Comparison of modeling techniques in circuit variability analysis
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields
Faster GPS via the sparse fourier transform
Proceedings of the 18th annual international conference on Mobile computing and networking
Power-efficient time-sensitive mapping in heterogeneous systems
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
A 0.5 V high-speed comparator with rail-to-rail input range
Analog Integrated Circuits and Signal Processing
Performance of CMOS and floating-gate full-adders circuits at subthreshold power supply
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Proceedings of the 20th International Conference on Real-Time and Network Systems
Symbolic modeling of a universal reconfigurable logic gate and its applications to circuit synthesis
Proceedings of the 2012 ACM Research in Applied Computation Symposium
Using DVFS to optimize time warp simulations
Proceedings of the Winter Simulation Conference
Design and Optimization of Multiplierless FIR Filters Using Sub-Threshold Circuits
Journal of Signal Processing Systems
Proceedings of the Conference on Design, Automation and Test in Europe
Biconditional BDD: a novel canonical BDD for logic synthesis targeting XOR-rich circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
An energy-efficient L2 cache architecture using way tag information under write-through policy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Semi-static threshold-triggered delay elements for low power operation
Analog Integrated Circuits and Signal Processing
Integration, the VLSI Journal
Graphics Processing Units and Open Computing Language for parallel computing
Computers and Electrical Engineering
Evolving spiking networks with variable resistive memories
Evolutionary Computation
Signal integrity and propagation delay analysis using FDTD technique for VLSI interconnects
Journal of Computational Electronics
| Hi-index | 0.02 |