Low-power clock branch sharing double-edge triggered flip-flop

Authors:
Peiyi Zhao;Jason McNeely;Pradeep Golconda;Magdy A. Bayoumi;Robert A. Barcenas;Weidong Kuang
Affiliations:
Integrated Circuit Design and Embedded System Laboratory, Math and Computer Science Department, Chapman University, Orange, CA;Center for Advanced Computer Studies, University of Louisiana at Lafayette, Lafayette, LA;Intel Corporation, Folsom, CA;Center for Advanced Computer Studies, University of Louisiana at Lafayette, Lafayette, LA;Integrated Circuit Design and Embedded System Laboratory, Math and Computer Science Department, Chapman University, Orange, CA;Department of Electrical Engineering, Pan American University, Edinburg, TX
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2007

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Abstract

In this paper, a new technique for implementing low-energy double-edge triggered flip-flops is introduced. The new technique employs a clock branch-sharing scheme to reduce the number of clocked transistors in the design. The newly proposed design also employs conditional discharge and split-path techniques to further reduce switching activity and short-circuit currents, respectively. As compared to the other state of the art double-edge triggered flip-flop designs, the newly proposed CBS_ip design has an improvement of up to 20% and 12.4% in view of power consumption and PDP, respectively.