A low-noise TTL-compatible CMOS off-chip driver circuit
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Automatic Verification of Mixed-Level Logic Circuits
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Power-Delay Metrics Revisited for 90nm CMOS Technology
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
FPGA clock network architecture: flexibility vs. area and power
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Novel Decoupling Capacitor Designs for sub- 90nm CMOS Technology
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
CMOS RF class-D power amplifier with bandpass sigma-delta modulation
Microelectronics Journal
Digital Circuit Optimization via Geometric Programming
Operations Research
Computing synchronizer failure probabilities
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 44th annual Design Automation Conference
Low-power clock branch sharing double-edge triggered flip-flop
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Block remap with turnoff: a variation-tolerant cache design technique
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
An accurate analytical crosstalk model for RC interconnect
CISST'08 Proceedings of the 2nd WSEAS International Conference on Circuits, Systems, Signal and Telecommunications
International Journal of Reconfigurable Computing - Regular issue
Avalanche breakdown in silicon devices for contactless logic testing and optical interconnect
Analog Integrated Circuits and Signal Processing
L-CBF: a low-power, fast counting bloom filter architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new family of sequential elements with built-in soft error tolerance for dual-VDD systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power clocked-pseudo-NMOS flip-flop for level conversion in dual supply systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interconnect power and delay optimization by dynamic programming in gridded design rules
Proceedings of the 19th international symposium on Physical design
Comparing forward and backward reachability as tools for safety analysis
HSCC'07 Proceedings of the 10th international conference on Hybrid systems: computation and control
Customizing pattern set for test power reduction via improved X-identification and reordering
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
A 12-bit 0.35 μm CMOS area optimized current-steering hybrid DAC
Analog Integrated Circuits and Signal Processing
Interconnect bundle sizing under discrete design rules
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Design of sequential elements for low power clocking system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hotspots elimination and temperature flattening in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Layout of decoupling capacitors in IP blocks for 90-nm CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Half-Rate Duobinary Transmitter Architecture for Chip-to-Chip Interconnect Applications
Analog Integrated Circuits and Signal Processing
TSV open defects in 3D integrated circuits: characterization, test, and optimal spare allocation
Proceedings of the 49th Annual Design Automation Conference
An inductive antenna mismatch recoverable RF power amplifier
Analog Integrated Circuits and Signal Processing
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The third edition of Hodges and Jackson's Analysis and Design of Digital Integrated Circuits has been thoroughly revised and updated by a new co-author, Resve Saleh of the University of British Columbia. The new edition combines the approachability and concise nature of the Hodges and Jackson classic with a complete overhaul to bring the book into the 21st century. The new edition has replaced the emphasis on Bipolar with an emphasis on CMOS. The book focuses on the latest CMOS technologies and uses standard deep submicron models throughout the book. The material on memory has been expanded and updated. As well the book now includes more on SPICE simulation and new problems that reflect recent technologies. The emphasis of the book is on design, but it does not neglect analysis and has as a goal to provide enough information so that a student can carry out analysis as well as be able to design a circuit. This book provides an excellent and balanced introduction to digital circuit design for both students and professionals. Table of contents 1 Deep Submicron Digital IC Design 2 MOS Transistors 3 Fabrication, Layout and Simulation 4 MOS Inverter Circuits 5 Static MOS Gate Circuits 6 High-Speed CMOS Logic Design 7 Transfer Gate and Dynamic Logic Design 8 Semiconductor Memory Design 9 Additional Topics in Memory Design 10 Interconnect Design 11 Power Grid and Clock Design Appendix A A Brief Introduction to Spice Appendix B Bipolar Transistors and Circuits