Fat-trees: universal networks for hardware-efficient supercomputing
IEEE Transactions on Computers
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Micronetwork-based integration for SOCs: 673
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Route packets, not wires: on-chip inteconnection networks
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Guest Editor's Introduction: What is Infrastructure IP?
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System-on-chip beyond the nanometer wall
Proceedings of the 40th annual Design Automation Conference
Interconnect IP Node for Future System-on-Chip Designs
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A Network on Chip Architecture and Design Methodology
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A Scalable Communication-Centric SoC Interconnect Architecture
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Analysis and Design of Digital Integrated Circuits
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Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Mesh-of-trees and alternative interconnection networks for single-chip parallelism
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Network-on-chip architecture design based on mesh-of-tree deterministic routing topology
International Journal of High Performance Systems Architecture
An analytical model for Network-on-Chip with finite input buffer
Frontiers of Computer Science in China
3D floorplanning of low-power and area-efficient Network-on-Chip architecture
Microprocessors & Microsystems
Clustered NOC, a suitable design for group communications in Network on Chip
Computers and Electrical Engineering
PACT '13 Proceedings of the 22nd international conference on Parallel architectures and compilation techniques
An analytical model for on-chip interconnects in multimedia embedded systems
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Multi-Processor (MP-SoC) platforms are emerging as the latest trend in SoC design. Monolithic bus-based interconnect architectures will not be able to support the clock cycle requirements of these high performance SoCs. Systems having multiple smaller buses, integrated through repeaters or bridges, are possible alternatives. But these kinds of solutions are ad-hoc in nature. By adopting a more structured network-based design paradigm, specific clock cycle requirements can easily be met. The precise focus of this paper is to show how the butterfly fat tree (BFT) can meet this objective when used as the overall MP-SoC interconnect architecture, thereby offering an attractive alternative for SoC interconnect that does not suffer from the non-scalability aspect of the buses in regards to the clock cycle.