Computer networks (3rd ed.)
A vision for embedded software
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs
ICCD '03 Proceedings of the 21st International Conference on Computer Design
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs
Proceedings of the 14th ACM Great Lakes symposium on VLSI
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
An Efficient Implementation of Distributed Routing Algorithms for NoCs
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Network Simplicity for Latency Insensitive Cores
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
A Performance Model of Communication in the Quarc NoC
ICPADS '08 Proceedings of the 2008 14th IEEE International Conference on Parallel and Distributed Systems
An Analysis of Reducing Communication Delay in Network-on-Chip Interconnect Architecture
Wireless Personal Communications: An International Journal
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In this paper, a Clustered NOC (C-NOC) is introduced to improve the performance of Hermes-NOC (H-NOC) in group communication. Each C-NOC switch has eight bi-directional ports connected to four neighbor switches and four local ports. With the same (IP) cores in both H-NOC and C-NOC networks, the ordinal size of C-NOC is 75% less than H-NOC. In corner-to-corner communication, C-NOC operates 29% faster than H-NOC. In random traffic mode, when the size of network is increased, then the average delay time of a packet in C-NOC is reached to this value in H-NOC. In group communication, a group of four IP cores is attached to a switch. The average delay time of a packet and number of clock pulses in C-NOC are 19.7% and 13.6% less than their values in H-NOC, respectively. This high performance of C-NOC is resulted from its internal switching. These comparisons in group communication show that C-NOC has superiority over H-NOC.