An Analysis of Reducing Communication Delay in Network-on-Chip Interconnect Architecture

Authors:
Hasan Furhad;Mohammad A. Haque;Cheol-Hong Kim;Jong-Myon Kim
Affiliations:
School of Electrical Engineering, University of Ulsan, Nam-Gu, Ulsan, South Korea 680-749;School of Electrical Engineering, University of Ulsan, Nam-Gu, Ulsan, South Korea 680-749;School of Electronics and Computer Engineering, Chonnam National University, Kwangju, South Korea 500-757;School of Electrical Engineering, University of Ulsan, Nam-Gu, Ulsan, South Korea 680-749
Venue:
Wireless Personal Communications: An International Journal
Year:
2013

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Abstract

This paper presents an Enhanced Clustered Mesh (EnMesh) topology for a Network-on-Chip architecture in order to reduce the communication delay between remote regions by considering the physical positions of remote nodes. EnMesh topology includes short paths between diagonal regions to ensure fast communication among remote nodes. The performance and silicon area overhead of EnMesh are analyzed and compared to those of state-of-the-art topologies such as Mesh, Torus, and Butterfly-Fat-Tree (BFT). Experimental results demonstrate that EnMesh outperforms other existing regular topologies in terms of throughput, latency, packet loss rate, and silicon area overhead.