A Router Architecture for Real-Time Communication in Multicomputer Networks
IEEE Transactions on Computers
A new switch chip for IBM RS/6000 SP systems
SC '99 Proceedings of the 1999 ACM/IEEE conference on Supercomputing
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Addressing the system-on-a-chip interconnect woes through communication-based design
Proceedings of the 38th annual Design Automation Conference
Micronetwork-based integration for SOCs: 673
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Powering networks on chips: energy-efficient and reliable interconnect design for SoCs
Proceedings of the 14th international symposium on Systems synthesis
A VLSI Architecture for Concurrent Data Structures
A VLSI Architecture for Concurrent Data Structures
The Alpha 21364 Network Architecture
IEEE Micro
IEEE Transactions on Parallel and Distributed Systems
Networks on Silicon: Blessing or Nightmare?
DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
Networks on Silicon: Combining Best-Effort and Guaranteed Services
Proceedings of the conference on Design, automation and test in Europe
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
Reducing test time with processor reuse in network-on-chip based systems
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Quality-of-service and error control techniques for mesh-based network-on-chip architectures
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Design space exploration and prototyping for on-chip multimedia applications
Proceedings of the 43rd annual Design Automation Conference
Linear-programming-based techniques for synthesis of network-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Benchmarking mesh and hierarchical bus networks in system-on-chip context
Journal of Systems Architecture: the EUROMICRO Journal
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The Power of Priority: NoC Based Distributed Cache Coherency
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Analysis and optimization of prediction-based flow control in networks-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Integration, the VLSI Journal
Power-Aware Real-Time Scheduling upon Dual CPU Type Multiprocessor Platforms
OPODIS '08 Proceedings of the 12th International Conference on Principles of Distributed Systems
Computers and Electrical Engineering
Evaluating SoC Network Performance in MPEG-4 Encoder
Journal of Signal Processing Systems
Best of both worlds: A bus enhanced NoC (BENoC)
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect
Fundamenta Informaticae - Application of Concurrency to System Design
A system-level design methodology for application-specific networks-on-chip
Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
Quality-of-service and error control techniques for mesh-based network-on-chip architectures
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Network-on-Chip Architectures for Neural Networks
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Leveraging application-level requirements in the design of a NoC for a 4G SoC: a case study
Proceedings of the Conference on Design, Automation and Test in Europe
Scalable network-on-chip architecture for configurable neural networks
Microprocessors & Microsystems
Static timing analysis for modeling QoS in networks-on-chip
Journal of Parallel and Distributed Computing
Dynamic decentralized mapping of tree-structured applications on NoC architectures
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect
Fundamenta Informaticae - Application of Concurrency to System Design
Power consumption and performance analysis of 3D NoCs
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
An Analysis of Reducing Communication Delay in Network-on-Chip Interconnect Architecture
Wireless Personal Communications: An International Journal
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Systems on Chip (SoCs) require efficient inter-module interconnection providing for the required communications at a low cost. We analyze the generic cost in area and power of Networks on Chip (NoCs) and alternative interconnect architectures: a shared bus, a segmented bus and a point-to-point interconnect. For each architecture we derive analytical expressions for area, power dissipation and operating frequency as well as asymptotic limits of these functions. The analysis quantifies the intuitive NoC scalability advantages.Next we turn to NoC cost optimization. We explore cost tradeoffs between the number of buffers and the link speed. We use a reference architecture, termed QNoC (Quality-of-Service NoC), which is based on a grid of wormhole switches, shortest path routing and multiple QoS classes. Two traffic scenarios are considered, one dominated by short packets sensitive to queuing delays and the other dominated by large block-transfers. Our simulations show that network cost can be minimized while maintaining quality of service, by trading off buffers with links in the first scenario but not in the second.