A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
System design based on single language and single-chip Java ASIP microcontroller
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Instruction-level DFT for testing processor and IP cores in system-on-a-chip
Proceedings of the 38th annual Design Automation Conference
Embedded Software-Based Self-Test for Programmable Core-Based Designs
IEEE Design & Test
System-on-chip beyond the nanometer wall
Proceedings of the 40th annual Design Automation Conference
A Study on Communication Issues for Systems-on-Chip
Proceedings of the 15th symposium on Integrated circuits and systems design
The Impact of NoC Reuse on the Testing of Core-based Systems
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
A Set of Benchmarks fo Modular Testing of SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Computer
SoCIN: A Parametric and Scalable Network-on-Chip
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Test data compression and test time reduction using an embedded microprocessor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Cost considerations in network on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time
IEICE - Transactions on Information and Systems
NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints
IEICE - Transactions on Information and Systems
Embedding Intelligence into EDA Tools
Proceedings of the 2006 conference on Integrated Intelligent Systems for Engineering Design
Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism
Journal of Electronic Testing: Theory and Applications
A practical test scheduling using network-based TAM in network on chip architecture
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
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This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores embedded into a system on chip. The resulting test time of the system is evaluated considering the number of reused processors, the number of external interfaces, and power dissipation. Experimental results for a set of industrial examples based on the ITC'02 benchmarks show that the cooperative use of both the on-chip network and the embedded processors can increase the test parallelism and reduce the test time.