Test cost reduction for SOCs using virtual TAMs and lagrange multipliers
Proceedings of the 40th annual Design Automation Conference
A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips
Journal of Electronic Testing: Theory and Applications
SOC test architecture design for efficient utilization of test bandwidth
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Computers
A Graph-Based Approach to Power-Constrained SOC Test Scheduling
Journal of Electronic Testing: Theory and Applications
Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Test Infrastructure Design for the Nexperia" Home Platform PNX8550 System Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Defect-Aware SOC Test Scheduling
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
A Note on System-on-Chip Test Scheduling Formulation
Journal of Electronic Testing: Theory and Applications
Improving mixed-signal SOC testing: a power-aware reuse-based approach with analog BIST
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Reducing test time with processor reuse in network-on-chip based systems
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Searching for Global Test Costs Optimization in Core-Based Systems
Journal of Electronic Testing: Theory and Applications
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Reusing an on-chip network for the test of core-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An improved test access mechanism structure and optimization technique in system-on-chip
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Hierarchy-aware and area-efficient test infrastructure design for core-based system chips
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Power-constrained test scheduling for multi-clock domain SoCs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Reuse-based test access and integrated test scheduling for network-on-chip
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Abort-on-fail based test scheduling
Journal of Electronic Testing: Theory and Applications
Test infrastructure design for mixed-signal SOCs with wrapped analog cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-chip test scheduling with reconfigurable core wrappers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs
IEEE Transactions on Computers
Optimized integration of test compression and sharing for SOC testing
Proceedings of the conference on Design, automation and test in Europe
Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers
Proceedings of the conference on Design, automation and test in Europe
Remote testing and diagnosis of System-on-Chips using network management frameworks
Proceedings of the conference on Design, automation and test in Europe
A robust protocol for concurrent on-line test (COLT) of NoC-based systems-on-a-chip
Proceedings of the 44th annual Design Automation Conference
SOC test architecture optimization for signal integrity faults on core-external interconnects
Proceedings of the 44th annual Design Automation Conference
Power-aware SoC test planning for effective utilization of port-scalable testers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Evolution of synthetic RTL benchmark circuits with predefined testability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Wafer-level modular testing of core-based SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of the test data volume reduction benefit of modular SOC testing
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Re-examining the use of network-on-chip as test access mechanism
Proceedings of the conference on Design, automation and test in Europe
Wrapper and TAM co-optimization for reuse of SoC functional interconnects
Proceedings of the conference on Design, automation and test in Europe
ACM Transactions on Design Automation of Electronic Systems (TODAES)
WSEAS Transactions on Circuits and Systems
Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Robust concurrent online testing of network-on-chip-based SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scheduling Power-Constrained Tests through the SoC Functional Bus
IEICE - Transactions on Information and Systems
Test Scheduling for Multi-Clock Domain SoCs under Power Constraint
IEICE - Transactions on Information and Systems
On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time
IEICE - Transactions on Information and Systems
NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints
IEICE - Transactions on Information and Systems
Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips
IEICE - Transactions on Information and Systems
Test-length and TAM optimization for wafer-level reduced pin-count testing of core-based SoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-Area Wrapper Cell Design for Hierarchical SoC Testing
Journal of Electronic Testing: Theory and Applications
Test Scheduling for Core-Based SOCs Using Genetic Algorithm Based Heuristic Approach
ICIC '07 Proceedings of the 3rd International Conference on Intelligent Computing: Advanced Intelligent Computing Theories and Applications. With Aspects of Artificial Intelligence
Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism
Journal of Electronic Testing: Theory and Applications
A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms
Journal of Parallel and Distributed Computing
SOC test planning using virtual test access architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Early estimation of wire length for dedicated test access mechanisms in networks-on-chip based SoCs
Proceedings of the 24th symposium on Integrated circuits and systems design
Optimization Methods for Post-Bond Testing of 3D Stacked ICs
Journal of Electronic Testing: Theory and Applications
Scheduling Tests for 3D Stacked Chips under Power Constraints
Journal of Electronic Testing: Theory and Applications
Test pin count reduction for NoC-based test delivery in multicore SOCs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Process-Variation and Temperature Aware SoC Test Scheduling Technique
Journal of Electronic Testing: Theory and Applications
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This paper presents the ITC'02 SOC Test Benchmarks. The purpose of this new benchmark set is to stimulate research into new methods and tools for modular testing of SOCs and to enable the objective comparison of such methods and tools with respect to effectiveness and efficiency. The paper defines the benchmark format and naming scheme, and presents the benchmark SOCs. In addition, it provides an overview of the research problems that can be addressed and evaluated by means of this benchmark set. These research problems include the design of optimized test access infrastructures and test schedules.