Optimal ordering of analog integrated circuit tests to minimize test time
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Defect-oriented test scheduling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-Constrained Test Scheduling for SoCs Under a "no session" Scheme
VLSI-SOC '01 Proceedings of the IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip: SOC Design Methodologies
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test wrapper and test access mechanism co-optimization for system-on-chip
Proceedings of the IEEE International Test Conference 2001
On Test Scheduling for Core-Based SOCs
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A Set of Benchmarks fo Modular Testing of SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D
ATS '01 Proceedings of the 10th Asian Test Symposium
Testing Reusable IP - A Case Study
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An Efficient Approach to SoC Wrapper Design, TAM Configuration and Test Scheduling
ETW '03 Proceedings of the 8th IEEE European Test Workshop
A retention-aware test power model for embedded SRAM
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Power constrained and defect-probability driven SoC test scheduling with test set partitioning
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Wafer-level modular testing of core-based SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Test-length and TAM optimization for wafer-level reduced pin-count testing of core-based SoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper we address the test scheduling problem forsystem-on-chip designs. Different from previous approacheswhere it is assumed that all tests will be performed untilcompletion, we consider the cases where the test processwill be terminated as soon as a defect is detected. This iscommon practice in production test of chips. The proposedtechnique takes into account the probability of defect-detectionby a test in order to schedule the tests so that theexpected total test time will be minimized. We investigatedifferent test bus structures, test scheduling strategies(sequential scheduling vs. concurrent scheduling), and testset assumptions (fixed test time vs. flexible test time). Wehave also made experiments to illustrate the efficiency oftaking defect probability into account during testscheduling.