A Unifying Methodology for Intellectual Property and Custom Logic Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
An IEEE 1149.1-Based Test Access Architecture for ICs with Embedded Cores
Proceedings of the IEEE International Test Conference
Test Requirements for Embedded Core-Based Systems and IEEE P1500
Proceedings of the IEEE International Test Conference
Modifying User-Defined Logic for Test Access to Embedded Cores
Proceedings of the IEEE International Test Conference
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
Proceedings of the IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing Embedded Cores Using Partial Isolation Rings
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
DAC '98 Proceedings of the 35th annual Design Automation Conference
System chip test: how will it impact your design?
Proceedings of the 37th Annual Design Automation Conference
Design of system-on-a-chip test access architectures under place-and-route and power constraints
Proceedings of the 37th Annual Design Automation Conference
CAS-BUS: a scalable and reconfigurable test access mechanisms for systems on a chip
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Testing TAPed cores and wrapped cores with the same test access mechanism
Proceedings of the conference on Design, automation and test in Europe
Optimal test access architectures for system-on-a-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test Bus Sizing for System-on-a-Chip
IEEE Transactions on Computers
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
Reusing Scan Chains for Test Pattern Decompression
Journal of Electronic Testing: Theory and Applications
On IEEE P1500's Standard for Embedded Core Test
Journal of Electronic Testing: Theory and Applications
On Concurrent Test of Core-Based SOC Design
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing
Journal of Electronic Testing: Theory and Applications
Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores
Journal of Electronic Testing: Theory and Applications
Constraint Driven Pin Mapping for Concurrent SOC Testing
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Genetic Algorithm based Test Scheduling and Test Access Mechanism Design for System-on-Chips
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
On Using IEEE P1500 SECT for Test Plug-n-Play
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Wrapper Design for Embedded Core Test
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An ILP Formulation to Optimize Test Access Mechanism in System-on-Chip Testing
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Space and Time Compaction Schemes for Embedded Cores
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips
Journal of Electronic Testing: Theory and Applications
Towards a Standard for Embedded Core Test: An Example
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Testing Reusable IP - A Case Study
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Addressable Test Ports An Approach to Testing Embedded Cores
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A Hierarchical Infrastructure for SoC Test Management
IEEE Design & Test
SOC test architecture design for efficient utilization of test bandwidth
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design of reconfigurable access wrappers for embedded core based SoC test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
IEEE Transactions on Computers
Wrapper Design for Testing IP Cores with Multiple Clock Domains
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Defect-Aware SOC Test Scheduling
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Searching for Global Test Costs Optimization in Core-Based Systems
Journal of Electronic Testing: Theory and Applications
Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
InTeRail: A Test Architecture for Core-Based SOCs
IEEE Transactions on Computers
Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs
IEEE Transactions on Computers
Power-constrained test scheduling for multi-clock domain SoCs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Abort-on-fail based test scheduling
Journal of Electronic Testing: Theory and Applications
Test infrastructure design for mixed-signal SOCs with wrapped analog cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-chip test scheduling with reconfigurable core wrappers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modular and rapid testing of SOCs with unwrapped logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test environment for embedded cores-based system-on-chip (soc): development and methodologies
MIC'06 Proceedings of the 25th IASTED international conference on Modeling, indentification, and control
Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs
IEEE Transactions on Computers
Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip
Integration, the VLSI Journal
Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers
Proceedings of the conference on Design, automation and test in Europe
SOC test architecture optimization for signal integrity faults on core-external interconnects
Proceedings of the 44th annual Design Automation Conference
A fully automated environment for verification of virtual prototypes
EURASIP Journal on Applied Signal Processing
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
Journal of Electronic Testing: Theory and Applications
On reliable modular testing with vulnerable test access mechanisms
Proceedings of the 45th annual Design Automation Conference
Analysis of the test data volume reduction benefit of modular SOC testing
Proceedings of the conference on Design, automation and test in Europe
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The efficient TAM design for core-based SOCs testing
WSEAS Transactions on Circuits and Systems
WSEAS Transactions on Circuits and Systems
An efficient scheduling algorithm based on multi-frequency tam for SOC testing
WSEAS Transactions on Circuits and Systems
MTNet: design of a wireless test framework for heterogeneous nanometer systems-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test Scheduling for Multi-Clock Domain SoCs under Power Constraint
IEICE - Transactions on Information and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-Area Wrapper Cell Design for Hierarchical SoC Testing
Journal of Electronic Testing: Theory and Applications
On-chip support for NoC-based SoC debugging
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Test-access mechanism optimization for core-based three-dimensional SOCs
Microelectronics Journal
Test architecture design and optimization for three-dimensional SoCs
Proceedings of the Conference on Design, Automation and Test in Europe
SOC test architecture and method for 3-D ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Effective diagnostic pattern generation strategy for transition-delay faults in full-scan SOCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wrapper design for multifrequency IP cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SOC test planning using virtual test access architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.02 |
This paper describes a structured test re-use methodologyand infrastructure for core-based system chips. The methodologyis based on the use of a structured test bus frameworkthat provides access to virtual components in asystem chip allowing the test methodologies and test vectorsfor these components to be re-used. It addresses thetest access, isolation, interconnect and shadow logic testproblems without requiring modifications to the components,even for cores with more ports than chip pins. Thetest area overhead required, including test bus routing, toimplement this methodology can be less than 1%.