The approximability of NP-hard problems
STOC '98 Proceedings of the thirtieth annual ACM symposium on Theory of computing
Self-test methodology for at-speed test of crosstalk in chip interconnects
Proceedings of the 37th Annual Design Automation Conference
Fault modeling and simulation for crosstalk in system-on-chip interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Improving bus test via IDDT and boundary scan
Proceedings of the 38th annual Design Automation Conference
Testing for interconnect crosstalk defects using on-chip embedded processor cores
Proceedings of the 38th annual Design Automation Conference
Built-in self-test for signal integrity
Proceedings of the 38th annual Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
An Integrated Framework for the Design and Optimization of SOC Test Solutions
Journal of Electronic Testing: Theory and Applications
Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems
IEEE Design & Test
Process Variations and their Impact on Circuit Operation
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
ATS '02 Proceedings of the 11th Asian Test Symposium
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
2.2 Signal Integrity Problems in Deep Submicron Arising from Interconnects between Cores
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
SOC Test Scheduling Using Simulated Annealing
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Test Resource Partitioning and Optimization for SOC Designs
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Testing SoC Interconnects for Signal Integrity Using Boundary Scan
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Wrapper Design for Embedded Core Test
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Embedded Core for Sub-Picosecond Timing Measurements
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A Set of Benchmarks fo Modular Testing of SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Effective and Efficient Test Architecture Design for SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Test Pattern Generation for Signal Integrity Faults on Long Interconnects
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Test Generation for Crosstalk-Induced Delay in Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Testing of Digital Systems
Test Infrastructure Design for the Nexperia" Home Platform PNX8550 System Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Multi.Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Time Domain Multiplexed TAM: Implementation and Comparison
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Multi-Frequency Test Access Mechanism Design for Modular SOC Testing
ATS '04 Proceedings of the 13th Asian Test Symposium
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Managing on-chip inductive effects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Crosstalk noise control in an SoC physical design flow
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Testing SoC interconnects for signal integrity using extended JTAG architecture
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Indirect test architecture for SoC testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multifrequency TAM design for hierarchical SOCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The test time for core-external interconnect shorts and opens is typically much less than that for core-internal logic. Therefore, prior work on test-infrastructure design for core-based system-on-a-chip (SOC) has mainly focused on minimizing the test time for core-internal logic. However, as feature sizes shrink for newer process technologies, the test time for signal integrity (SI) faults on interconnects cannot be neglected. The test time for SI faults can be comparable to, or even larger than, the test time for the embedded cores. We investigate the impact of interconnect SI tests on SOC test-architecture design and optimization. A compaction method for SI faults and algorithms for test-architecture optimization are also presented. Experimental results for the ITC'02 benchmarks show that the proposed approach can significantly reduce the overall testing time for core-internal logic and core-external interconnects.