Managing on-chip inductive effects

Authors:
Y. Massoud;S. Majors;J. Kawa;T. Bustami;D. MacMillen;J. White
Affiliations:
Synopsys Inc., Mountain View, CA, USA;-;-;-;-;-
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2002

Citing 0
Cited 13

A CAD Methodology and Tool for the Characterization of Wide On-Chip Buses

Proceedings of the conference on Design, automation and test in Europe - Volume 3
Controlling Inductive Coupling in Wide Global Signal Busses Through Swizzling

Analog Integrated Circuits and Signal Processing
Shielding area optimization under the solution of interconnect crosstalk

Journal of Computer Science and Technology
Modeling and design challenges and solutions for carbon nanotube-based interconnect in future high performance integrated circuits

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Assessing carbon nanotube bundle interconnect for future FPGA architectures

Proceedings of the conference on Design, automation and test in Europe
SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Accurate loop self inductance bound for efficient inductance screening

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing signal timing variations in inter-core busses

Integration, the VLSI Journal
Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network

NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
Exponentially tapered h-tree clock distribution networks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the impact of on-chip inductance on signal nets under the influence of power grid noise

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and modeling of energy consumption in RLC tree circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-aggressor capacitive and inductive coupling noise modeling and mitigation

Microelectronics Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

With process technology and functional integration advancing steadily, chips are continuing to grow in area while critical dimensions are shrinking. This has led to the emergence of on-chip inductance to be a factor whose effect on performance and on signal integrity has to be managed by chip designers and has to be sometimes traded off against other performance parameters. In this paper, we cover several techniques to reduce on-chip inductance which in turn improve timing predictability and reduce signal delay and crosstalk noise. We present experimental results obtained from simulations of a typical high performance bus structure and a clock tree structure to examine the effectiveness of some of the different inductance reduction techniques.