Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network

Authors:
Yuan Xie;Soumya Eachempati;Aditya Yanamandra;Vijaykrishnan Narayanan;Mary Jane Irwin
Affiliations:
Dept. of Computer Science and Engineering, Pennsylvania State University, University Park, USA;Dept. of Computer Science and Engineering, Pennsylvania State University, University Park, USA;Dept. of Computer Science and Engineering, Pennsylvania State University, University Park, USA;Dept. of Computer Science and Engineering, Pennsylvania State University, University Park, USA;Dept. of Computer Science and Engineering, Pennsylvania State University, University Park, USA
Venue:
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
Year:
2009

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Abstract

The gigahertz frequency regime together with the rising delay of on-chip interconnect and increased device densities, has resulted in aggravating clock skew problem. Skew and power dissipation of clock distribution networks are key factors in determining the maximum attainable clock frequency as well as the chip power consumption. The traditional skew balancing schemes incur additional cost of increased area and power. In this paper, we propose a novel skew reduction mechanism using dissimilar interconnect materials for balancing the non-uniform loads in a clock network. Single walled carbon nanotube (SWCNT) bundles have been shown to have high electrical conductivity for future process technology nodes. We design a H-tree clock network made up of both SWCNT bundles and copper interconnect at 22nm technology node. Our experiments show that such a network saves an average of 65% in area and 22% of power over a pure copper distribution network.