IEEE Transactions on Computers
Reliable non-zero skew clock trees using wire width optimization
DAC '93 Proceedings of the 30th international Design Automation Conference
Process-variation-tolerant clock skew minimization
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Post routing performance optimization via multi-link insertion and non-uniform wiresizing
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Sizing of clock distribution networks for high performance CPU chips
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Optimal clock skew scheduling tolerant to process variations
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Bounded-skew clock and Steiner routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Impact of interconnect variations on the clock skew of a gigahertz microprocessor
Proceedings of the 37th Annual Design Automation Conference
Hybrid structured clock network construction
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Power Supply Noise Suppression via Clock Skew Scheduling
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
A Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Reducing clock skew variability via cross links
Proceedings of the 41st annual Design Automation Conference
A multiple level network approach for clock skew minimization with process variations
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Clock skew verification in the presence of IR-drop in the power distribution network
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reducing clock skew variability via cross links
Proceedings of the 41st annual Design Automation Conference
Improved algorithms for link-based non-tree clock networks for skew variability reduction
Proceedings of the 2005 international symposium on Physical design
Variation tolerant buffered clock network synthesis with cross links
Proceedings of the 2006 international symposium on Physical design
Efficient Model Update for General Link-Insertion Networks
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Clock Distribution Architectures: A Comparative Study
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
DiCER: distributed and cost-effective redundancy for variation tolerance
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical based link insertion for robust clock network design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Practical techniques to reduce skew and its variations in buffered clock networks
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Impact of Thermal Gradients on Clock Skew and Testing
IEEE Design & Test
An efficent clustering algorithm for low power clock tree synthesis
Proceedings of the 2007 international symposium on Physical design
Combinatorial algorithms for fast clock mesh optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Discrete buffer and wire sizing for link-based non-tree clock networks
Proceedings of the 2008 international symposium on Physical design
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A novel scheme to reduce short-circuit power in mesh-based clock architectures
Proceedings of the 21st annual symposium on Integrated circuits and system design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Proceedings of the 2009 international symposium on Physical design
Power efficient tree-based crosslinks for skew reduction
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Low-power rotary clock array design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Combinatorial algorithms for fast clock mesh optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Clock skew optimization considering complicated power modes
Proceedings of the Conference on Design, Automation and Test in Europe
Discrete buffer and wire sizing for link-based non-tree clock networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Meshworks: a comprehensive framework for optimized clock mesh network synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
On old and new routing problems
Proceedings of the 2011 international symposium on Physical design
Cross link insertion for improving tolerance to variations in clock network synthesis
Proceedings of the 2011 international symposium on Physical design
Synthesis of low power clock trees for handling power-supply variations
Proceedings of the 2011 international symposium on Physical design
Proceedings of the 2011 international symposium on Physical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multilevel tree fusion for robust clock networks
Proceedings of the International Conference on Computer-Aided Design
Local clock skew minimization using blockage-aware mixed tree-mesh clock network
Proceedings of the International Conference on Computer-Aided Design
Resource-constrained link insertion for delay reduction
Integration, the VLSI Journal
Fast timing analysis of clock networks considering environmental uncertainty
Integration, the VLSI Journal
SPECO: Stochastic Perturbation based Clock tree Optimization considering temperature uncertainty
Integration, the VLSI Journal
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Local merges for effective redundancy in clock networks
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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Increasingly significant variational effects present a great challenge for delivering desired clock skew reliably. Non-tree clock network has been recognized as a promising approach to overcome the variation problem. Existing non-tree clock routing methods are restricted to a few simple or regular structures, and often consume excessive amount of wire-length. In this paper, we suggest to construct a low cost non-tree clock network by inserting cross links in a given clock tree. The effects of the link insertion on clock skew variability are analyzed. Based on the analysis, we propose two link insertion schemes that can quickly convert a clock tree to a non-tree with significantly lower skew variability and very limited wirelength increase. In these schemes, the complicated non-tree delay computation is circumvented. Further, they can be applied to the recently popular non-zero skew routing easily. Experimental results on benchmark circuits show that this approach can achieve significant skew variability reduction with less than 2 increase of wirelength.