Clock-skew test module for exploring reliable clock-distribution under process and global voltage-temperature variations

Authors:
Kan Takeuchi;Atsushi Yoshikawa;Michio Komoda;Ken Kotani;Hiroaki Matsushita;Yusaku Katsuki;Yuyo Yamamoto;Takao Sato
Affiliations:
Renesas Technology Corporation, Tokyo, Japan;Renesas Technology Corporation, Tokyo, Japan;Renesas Technology Corporation, Tokyo, Japan;Renesas Technology Corporation, Tokyo, Japan;Renesas Technology Corporation, Tokyo, Japan;Hitachi ULSI Systems Company Ltd., Fukuoka, Japan;Hitachi ULSI Systems Company Ltd., Fukuoka, Japan;Hitachi ULSI Systems Company Ltd., Fukuoka, Japan
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2008

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Abstract

This paper presents a clock-skew test module for exploring reliable clock distribution under process, voltage, and temperature (PVT) variations. The proposed test module enables direct evaluation of the following two important issues: 1) the clock-skew process variations and 2) the robustness against race problems under environmental variations such as voltages and temperatures. The test module was fabricated by using a 90-nm low-power process for system-on-chip (SoC). It contains eight blocks including H-tree blocks and clock tree synthesis (CTS)-tree blocks (i.e., blocks formed by clock-tree synthesis), each of which has 1024 flip-flop (FF) pairs with small hold-time margins. A statistical method has been developed for analyzing the measured hold-time margins of the 1024 FF pairs for 80 chips. The example of the analysis for the measured results is presented, confirming the effectiveness of the proposed test module and analysis method toward reliable design of clock distribution.