A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance

Authors:
Vikas Mehrotra;Shiou Lin Sam;Duane Boning;Anantha Chandrakasan;Rakesh Vallishayee;Sani Nassif
Affiliations:
Massachusetts Institute of Technology, Cambridge, MA;Massachusetts Institute of Technology, Cambridge, MA;Massachusetts Institute of Technology, Cambridge, MA;Massachusetts Institute of Technology, Cambridge, MA;PDF Solutions, San Jose, CA;IBM, Austin, TX
Venue:
Proceedings of the 37th Annual Design Automation Conference
Year:
2000

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Abstract

We present a methodology to study the impact of spatial pattern dependent variation on circuit performance and implement the technique in a CAD framework. We investigate the effects of interconnect CMP and poly CD device variation on interconnect delay and clock skew in both aluminum and copper interconnect technology. Our results indicate that interconnect CMP variation strongly affects interconnect delay, while poly CD variation has a large impact on clock skew in a 1 GHz design. Given this circuit impact, CAD tools in the future must account for such systematic within-die variations.