Numerical techniques for stochastic optimization
Numerical techniques for stochastic optimization
Proceedings of the 37th Annual Design Automation Conference
Impact of RET on physical layouts
Proceedings of the 2001 international symposium on Physical design
Reticle enhancement technology: implications and challenges for physical design
Proceedings of the 38th annual Design Automation Conference
Layout design methodolgies for sub-wavelength manufacturing
Proceedings of the 38th annual Design Automation Conference
Adoption of OPC and the impact on design and layout
Proceedings of the 38th annual Design Automation Conference
Uncertainty-aware circuit optimization
Proceedings of the 39th annual Design Automation Conference
A general probabilistic framework for worst case timing analysis
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Statistical timing analysis using bounds and selective enumeration
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Layout impact of resolution enhancement techniques: impediment or opportunity?
Proceedings of the 2003 international symposium on Physical design
Advanced routing in changing technology landscape
Proceedings of the 2003 international symposium on Physical design
Research directions for coevolution of rules and routers
Proceedings of the 2003 international symposium on Physical design
A cost-driven lithographic correction methodology based on off-the-shelf sizing tools
Proceedings of the 40th annual Design Automation Conference
Performance-impact limited area fill synthesis
Proceedings of the 40th annual Design Automation Conference
Death, taxes and failing chips
Proceedings of the 40th annual Design Automation Conference
Exploring regular fabrics to optimize the performance-cost trade-off
Proceedings of the 40th annual Design Automation Conference
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Proceedings of the 2005 international symposium on Physical design
Technology migration technique for designs with strong RET-driven layout restrictions
Proceedings of the 2005 international symposium on Physical design
Self-Compensating Design for Focus Variation
Proceedings of the 42nd annual Design Automation Conference
RADAR: RET-aware detailed routing using fast lithography simulations
Proceedings of the 42nd annual Design Automation Conference
Deployment of Better Than Worst-Case Design: Solutions and Needs
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Maze routing with OPC consideration
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Detailed placement for improved depth of focus and CD control
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
The impact of the nanoscale on computing systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Ultra low-cost defect protection for microprocessor pipelines
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Architecting a reliable CMP switch architecture
ACM Transactions on Architecture and Code Optimization (TACO)
Technology migration techniques for simplified layouts with restrictive design rules
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Buffering global interconnects in structured ASIC design
Integration, the VLSI Journal
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Design rule optimization of regular layout for leakage reduction in nanoscale design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Wire sizing and spacing for lithographic printability and timing optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dose map and placement co-optimization for timing yield enhancement and leakage power reduction
Proceedings of the 45th annual Design Automation Conference
On modeling and testing of lithography related open faults in nano-CMOS circuits
Proceedings of the conference on Design, automation and test in Europe
Redundant wire insertion for yield improvement
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Simple and accurate models for capacitance considering floating metal fill insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dose map and placement co-optimization for improved timing yield and leakage power
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Leakage reduction through optimization of regular layout parameters
Microelectronics Journal
Design and Analysis of a Robust Carbon Nanotube-Based Asynchronous Primitive Circuit
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A novel statistical and circuit-based technique for counterfeit detection in existing ICs
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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Ultra-deep submicron manufacturability impacts physicaldesign (PD) through complex layout rules and large guardbands for process variability; this creates new requirements for new manufacturing-aware PD technologies. The firstpart of this tutorial reviews PD complications and methodology changes - notably in the detailed routing arena - that arise from subwavelength lithography and deep-submicronmanufacturing (antennas, metal planarization and mask-wafer mismatch). Process variations and their sources are taxonomized for modeling and simulation. A framework ofdesign for cost and value is described. The second part covers yield-constrained optimizations in PD, especially "beyond corners" approaches that escape today's pessimistic or even incorrect corner-based approaches. Statistical timingand noise analyses enable optimization of parametric yieldand reliability. Yield-aware cell libraries and "analog" design rules (as opposed to "digital", 0/1 rules) can help designers explore yield-cost tradeoffs, especially for low-volumeparts. We then examine performance impact-limited fill insertion which goes beyond mere capacitance rules. Modeling, objectives, and filling strategies are discussed. Finally,we discuss current and near-term prospects for the overall design-to-manufacturing PD methodology. Key aspects include better integrations with analysis and manufacturing interfaces, as well as cost-benefit tradeoffs for "regular"layout structures that are likely beyond 90nm, cost optimizations for low-volume production, and the role of robust and/or stochastic optimization in PD.