Reticle enhancement technology: implications and challenges for physical design
Proceedings of the 38th annual Design Automation Conference
Performance-impact limited area fill synthesis
Proceedings of the 40th annual Design Automation Conference
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Manufacturing-Aware Physical Design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Study of Floating Fill Impact on Interconnect Capacitance
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
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In this paper, we analyze and model the impact of floating dummy fill on the signal capacitance considering various parameters including signal dimensions, dummy shape and dimensions. Intra-layer dummy has its greatest impact on coupling capacitance while interlayer dummy has larger impact on the ground capacitance component. Based on this analysis, we propose simple capacitance models (Cc for intra-layer dummy and Cg for inter-layer dummy). To consider realistic cases with both signals and metal fill in adjacent layers, we apply a weighting function approach to the Cg model. We verify this model using benchmark circuits and find that total net capacitance with floating fill can be extracted within ∼ 1% of field solver results on average with total extraction runtime reductions of up to 40%. When evaluating the incremental capacitance due to fill alone, average error of the models range from 2%-15% across benchmarks and fill-related runtime overhead is reduced by 60%-88%.