Study of Floating Fill Impact on Interconnect Capacitance

Authors:
Andrew B. Kahng;Kambiz Samadi;Puneet Sharma
Affiliations:
UCSD CSE and ECE Departments, La Jolla, CA;UCSD ECE Department, La Jolla, CA;UCSD ECE Department, La Jolla, CA
Venue:
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Year:
2006

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Abstract

It is well known that fill insertion adversely affects total and coupling capacitance of interconnects. While grounded fill can be extracted by full-chip extractors, floating fill can be reliably extracted by 3D field solvers only. Due to poor understanding of the impact of floating fill on capacitance, designers insert floating fill conservatively. In this paper we study the impact of floating fill insertion on coupling and total capacitance when the fill geometry, and both the interconnects between which the capacitance is measured are on the same layer. We show that the capacitance with same-layer neighboring interconnects is a large fraction of total capacitance, and that it is significantly affected by fill geometries on the same layer. We analyze the effect of fill configuration parameters such as fill size, fill location, interconnect width, interconnect spacing, etc. and consider edge effects and effects occurring due to insertion of several fill geometries in close proximity. Based on our findings, we propose certain guidelines to achieve high metal density while having smaller impact on interconnect capacitance. Finally, we validate the proposed guidelines using representative process parameters and a 3D field solver. On average coupling capacitance increase due to floating-fill insertion decreases by ~ 53% on using the proposed guidelines.