Computational geometry: an introduction
Computational geometry: an introduction
Filling and Scotting: Analysis and Algorithms
Filling and Scotting: Analysis and Algorithms
Subwavelength optical lithography: challenges and impact on physical design
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Optimal phase conflict removal for layout of dark field alternating phase shifting masks
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Subwavelength lithography and its potential impact on design and EDA
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Monte-Carlo algorithms for layout density control
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Closing the smoothness and uniformity gap in area fill synthesis
Proceedings of the 2002 international symposium on Physical design
Research directions for coevolution of rules and routers
Proceedings of the 2003 international symposium on Physical design
Study of Floating Fill Impact on Interconnect Capacitance
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Is your layout density verification exact?: a fast exact algorithm for density calculation
Proceedings of the 2007 international symposium on Physical design
Dummy fill optimization for enhanced manufacturability
Proceedings of the 19th international symposium on Physical design
On linewidth-based yield analysis for nanometer lithography
Proceedings of the Conference on Design, Automation and Test in Europe
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In very deep-submicron VLSI, certain manufacturing steps &mdash notably optical exposure, resist development and etch, chemical vapor deposition and chemical-mechanical polishing (CMP)&mdash have varying effects on device and interconnect features depending on local characteristics of the layout. To make these effects uniform and predictable, the layout itself must be made uniform with respect to certain density parameters. Traditionally, only foundries have performed the post-processing needed to achieve this uniformity, via insertion (“filling”) or partial deletion (“slotting”) of features in the layout. Today, however, physical design and verification tools cannot remain oblivious to such foundry post-processing. Without an accurate estimate of the filling and slotting, RC extraction, delay calculation, and timing and noise analysis flows will all suffer from wild inaccuracies. Therefore, future place-and-route tools must efficiently perform filling and slotting prior to performance analysis within the layout optimization loop. We give the first formulations of the filling and slotting problems that arise in layout post-processing or layout optimization for manufacturability. Such formulations seek to add or remove features to a given process layer, so that the local area or perimeter density of features satisfies prescribed upper and lower bounds in all windows of a given size. We also present efficient algorithms for density analysis as well as for filling/slotting synthesis. Our work provides a new unification between manufacturing and physical design, and captures a number of general requirements imposed on layout by the manufacturing process.