Filling and slotting: analysis and algorithms
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Multilevel full-chip routing with testability and yield enhancement
Proceedings of the 2005 international workshop on System level interconnect prediction
Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design
Proceedings of the 2005 international symposium on Physical design
FastRoute: a step to integrate global routing into placement
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Wire density driven global routing for CMP variation and timing
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
CMP-aware Maze Routing Algorithm for Yield Enhancement
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
The ISPD global routing benchmark suite
Proceedings of the 2008 international symposium on Physical design
Full-chip routing system for reducing Cu CMP & ECP variation
Proceedings of the 21st annual symposium on Integrated circuits and system design
NTHU-Route 2.0: a fast and stable global router
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A novel wire-density-driven full-chip routing system for CMP variation control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CMP Fill Synthesis: A Survey of Recent Studies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Congestion-Constrained Layer Assignment for Via Minimization in Global Routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Techniques for scalable and effective routability evaluation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper presents a router that minimizes the amount of dummy fill necessary to satisfy the requirements for chemical-mechanical polishing (CMP). The algorithm uses a greedy strategy and effective cost functions to control the maximal effective pattern density during routing. On a standard set of benchmark circuits, our CMP-aware router can reduce the required dummy fill by 22.0% on average, and up to 41.5%, as compared to the CMP-unaware case. In comparison with another CMP-aware routing approach, our algorithm is demonstrated to reduce the amount of dummy fill by 14.1% on average, and up to 23.6%, over the benchmarks.