Timing driven placement for large standard cell circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Timing driven placement in interaction with netlist transformations
Proceedings of the 1997 international symposium on Physical design
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Estimating routing congestion using probabilistic analysis
Proceedings of the 2001 international symposium on Physical design
Timing driven placement using physical net constraints
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Accurate pseudo-constructive wirelength and congestion estimation
Proceedings of the 2003 international workshop on System-level interconnect prediction
Timing-driven placement using design hierarchy guided constraint generation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Improved global routing through congestion estimation
Proceedings of the 40th annual Design Automation Conference
Probabilistic congestion prediction
Proceedings of the 2004 international symposium on Physical design
Is probabilistic congestion estimation worthwhile?
Proceedings of the 2005 international workshop on System level interconnect prediction
Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design
Proceedings of the 2005 international symposium on Physical design
Global routing by new approximation algorithms for multicommodity flow
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An effective congestion-driven placement framework
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IPR: an integrated placement and routing algorithm
Proceedings of the 44th annual Design Automation Conference
Archer: a history-driven global routing algorithm
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
High-performance routing at the nanometer scale
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
BoxRouter 2.0: architecture and implementation of a hybrid and robust global router
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Sidewinder: a scalable ILP-based router
Proceedings of the 2008 international workshop on System level interconnect prediction
An O(nlogn) edge-based algorithm for obstacle-avoiding rectilinear steiner tree construction
Proceedings of the 2008 international symposium on Physical design
Proceedings of the 2008 international symposium on Physical design
The coming of age of (academic) global routing
Proceedings of the 2008 international symposium on Physical design
MaizeRouter: engineering an effective global router
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A new global router for modern designs
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Congestion prediction in early stages of physical design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
NTHU-Route 2.0: a fast and stable global router
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
FastRoute3.0: a fast and high quality global router based on virtual capacity
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
FastRoute 4.0: global router with efficient via minimization
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
On improving optimization effectiveness in interconnect-driven physical synthesis
Proceedings of the 2009 international symposium on Physical design
An O(n log n) path-based obstacle-avoiding algorithm for rectilinear Steiner tree construction
Proceedings of the 46th Annual Design Automation Conference
Detailed-routing algorithms for dense pin clusters in integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Archer: a history-based global routing algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Obstacle-avoiding rectilinear Steiner tree construction based on Steiner point selection
Proceedings of the 2009 International Conference on Computer-Aided Design
Exact route matching algorithms for analog and mixed signal integrated circuits
Proceedings of the 2009 International Conference on Computer-Aided Design
GRPlacer: improving routability and wire-length of global routing with circuit replacement
Proceedings of the 2009 International Conference on Computer-Aided Design
A multilevel congestion-based global router
VLSI Design
Completing high-quality global routes
Proceedings of the 19th international symposium on Physical design
Dummy fill optimization for enhanced manufacturability
Proceedings of the 19th international symposium on Physical design
Multilayer global routing with via and wire capacity considerations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pulsed-latch aware placement for timing-integrity optimization
Proceedings of the 47th Design Automation Conference
NTHU-route 2.0: a robust global router for modern designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Cut-demand based routing resource allocation and consolidation for routability enhancement
Proceedings of the 16th Asia and South Pacific Design Automation Conference
An enhanced global router with consideration of general layer directives
Proceedings of the 2011 international symposium on Physical design
Reliability-Driven Power/Ground Routing for Analog ICs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An auction based pre-processing technique to determine detour in global routing
Proceedings of the International Conference on Computer-Aided Design
GLADE: a modern global router considering layer directives
Proceedings of the International Conference on Computer-Aided Design
Routability-driven placement algorithm for analog integrated circuits
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
GDRouter: interleaved global routing and detailed routing for ultimate routability
Proceedings of the 49th Annual Design Automation Conference
GLARE: global and local wiring aware routability evaluation
Proceedings of the 49th Annual Design Automation Conference
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
SRP: simultaneous routing and placement for congestion refinement
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Ripple 2.0: high quality routability-driven placement via global router integration
Proceedings of the 50th Annual Design Automation Conference
Routability optimization for crossbar-switch structured ASIC design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Techniques for scalable and effective routability evaluation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Because of the increasing dominance of interconnect issues in advanced IC technology, placement has become a critical step in the IC design flow. To get accurate interconnect information during the placement process, it is desirable to incorporate global routing into it. However, previous global routers are computationally expensive. It is impractical to perform global routing repeatedly during placement. In this paper, we present an extremely fast and high-quality global router called FastRoute. In traditional global routing approaches, congestion is not considered during Steiner tree construction. So they have to rely on the time-consuming maze routing technique to eliminate routing congestion. Different from traditional approaches, we proposed a congestion-driven Steiner tree topology generation technique and an edge shifting technique to determine the good Steiner tree topologies and Steiner node positions. Based on the congestion-driven Steiner trees, we only need to apply maze routing to a small percentage of the two-pin nets once to obtain high quality global routing solutions. We also proposed a new cost function based on logistic function to direct the maze routing. Experimental results show that FastRoute generates less congested solutions in 132x and 64x faster runtimes than the state-of-the-art academic global routers Labyrinth [1] and Chi Dispersion router [2], respectively. It is even faster than the highly-efficient congestion estimator FaDGloR [3]. The promising results make it possible to incorporate global routing directly into placement process without much runtime penalty. This could dramatically improve the placement solution quality. We believe this work will fundamentally change the way the EDA community look at and make use of global routing in the whole design flow.