Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Module placement for analog layout using the sequence-pair representation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Block placement with symmetry constraints based on the O-tree non-slicing representation
Proceedings of the 37th Annual Design Automation Conference
Analog Device-Level Layout Automation
Analog Device-Level Layout Automation
Modeling non-slicing floorplans with binary trees
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Placement with symmetry constraints for analog layout design using TCG-S
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Analog placement with symmetry and other placement constraints
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
FastRoute: a step to integrate global routing into placement
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Analog placement based on novel symmetry-island formulation
Proceedings of the 44th annual Design Automation Conference
Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Analog placement with common centroid constraints
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Analog placement based on hierarchical module clustering
Proceedings of the 45th annual Design Automation Conference
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
NTHU-Route 2.0: a fast and stable global router
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Analog placement with common centroid and 1-D symmetry constraints
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Thermal-driven analog placement considering device matching
Proceedings of the 46th Annual Design Automation Conference
Performance-driven analog placement considering boundary constraint
Proceedings of the 47th Design Automation Conference
Analog layout synthesis: recent advances in topological approaches
Proceedings of the Conference on Design, Automation and Test in Europe
Practical placement and routing techniques for analog circuit designs
Proceedings of the International Conference on Computer-Aided Design
FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LASER: layout-aware analog synthesis environment on laker
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Simultaneous analog placement and routing with current flow and current density considerations
Proceedings of the 50th Annual Design Automation Conference
Efficient analog layout prototyping by layout reuse with routing preservation
Proceedings of the International Conference on Computer-Aided Design
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To obtain good layout quality and reliability, placement is a very important stage during the physical design of analog circuits. Many works have been proposed to consider topological constraints for analog placement, and they devote to generate compact placements to minimize area and wirelength. However, a compact placement may induce unwanted routing issues. In order to reduce parasitics and cross-talk effects during the routing phase, wires are preferred not to pass above the active area of analog devices. Therefore, it is required to preserve enough routing spaces between devices for successful routing. Currently, there exists limited works studying routability for analog placement, but none of these works consider that symmetry property must be maintained during placement expansion. In this paper, we present a two-stage routability-driven analog placer based on ASF-B*-tree and HB*-tree representations. To reduce running time, our placement algorithm first generates a compact placement to minimize wirelength and area without considering congestion problem. Then, routing congestion regions are expanded locally to resolve the routability problem. Most importantly, the symmetry property of analog placement is always satisfied during the expansion process. Experimental results show that our analog placer can effectively minimize routing congestion without violating the symmetry property after placement expansion.