Module placement on BSG-structure and IC layout applications
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A new area and shape function estimation technique for VLSI layouts
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Block placement with symmetry constraints based on the O-tree non-slicing representation
Proceedings of the 37th Annual Design Automation Conference
Corner block list: an effective and efficient topological representation of non-slicing floorplan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
The sizing rules method for analog integrated circuit design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Improved method of cell placement with symmetry constraints for analog IC layout design
Proceedings of the 2006 international symposium on Physical design
Analog placement with symmetry and other placement constraints
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Analog placement based on novel symmetry-island formulation
Proceedings of the 44th annual Design Automation Conference
Analog placement with common centroid constraints
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Sizing rules for bipolar analog circuit design
Proceedings of the conference on Design, automation and test in Europe
Automation of IC layout with analog constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Symmetry within the sequence-pair representation in the context of placement for analog design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the exploration of the solution space in analog placement with symmetry constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
TCG-S: orthogonal coupling of P*-admissible representations for general floorplans
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Thermal-driven analog placement considering device matching
Proceedings of the 46th Annual Design Automation Conference
Automatic generation of hierarchical placement rules for analog integrated circuits
Proceedings of the 19th international symposium on Physical design
Performance-driven analog placement considering boundary constraint
Proceedings of the 47th Design Automation Conference
Analog layout synthesis: recent advances in topological approaches
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the 48th Design Automation Conference
A corner stitching compliant B*-tree representation and its applications to analog placement
Proceedings of the International Conference on Computer-Aided Design
Practical placement and routing techniques for analog circuit designs
Proceedings of the International Conference on Computer-Aided Design
Routability-driven placement algorithm for analog integrated circuits
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
LAYGEN II: automatic analog ICs layout generator based on a template approach
Proceedings of the 14th annual conference on Genetic and evolutionary computation
Performance-driven analog placement considering monotonic current paths
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
Area optimization on fixed analog floorplans using convex area functions
Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
The analog placement algorithm Plantage, presented in this paper, generates placements for analog circuits with comprehensive placement constraints. Plantage is based on a hierarchically bounded enumeration of basic building blocks, using B*-trees. The practically relevant solution space is thereby enumerated quasi-complete. The sets of possible placements of the basic building blocks are represented and combined in a new efficient way, using enhanced shape functions. The result of Plantage is the Pareto front of placements with respect to different aspect ratios. The whole approach is deterministic, in contrast to existing analog placement algorithms.