Measurement and modeling of MOS transistor current mismatch in analog IC's
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Automatic Generation of Common-Centroid Capacitor Arrays with Arbitrary Capacitor Ratio
Proceedings of the conference on Design, automation and test in Europe
Analog placement with common centroid constraints
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Analog placement with common centroid and 1-D symmetry constraints
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Yield evaluation of analog placement with arbitrary capacitor ratio
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Thermal-driven analog placement considering device matching
Proceedings of the 46th Annual Design Automation Conference
Placement optimization for yield improvement of switched-capacitor analog integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 48th Design Automation Conference
Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Switched capacitors are commonly used in analog design. The circuit performance based on this technique relies on the accuracy of capacitance ratios, which are affected by random and systematic mismatches. To meet the accuracy requirement, designers can increase the layout area of unit capacitors to reduce random mismatch. Since increasing layout area enlarges the distance between unit capacitors, it induces more gradient errors, which results in larger systematic mismatch. Therefore, the better way for reducing the gradient errors is to carefully determine the locations of unit capacitors in a capacitor array. Moreover, the resulting placement must have high capacitance correlation in order to enhance yield. In this paper, we first explore the attributes of a good capacitor placement, which can reduce gradient errors and increase capacitance correlation. Then, an analytical-based approach is proposed to complete capacitor placement considering these issues. Finally, the results are optimized by arbitrarily swapping two unit capacitors. Compared with the simulated annealing based approach, the proposed method not only achieves better placement results but also gets 34x faster for the largest benchmark capacitor array.