Measurement and modeling of MOS transistor current mismatch in analog IC's
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Automatic Generation of Common-Centroid Capacitor Arrays with Arbitrary Capacitor Ratio
Proceedings of the conference on Design, automation and test in Europe
Evaluation of Capacitor Ratios in Automated Accurate Common-Centroid Capacitor Arrays
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Analog placement with common centroid constraints
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Analog placement with common centroid and 1-D symmetry constraints
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Yield evaluation of analog placement with arbitrary capacitor ratio
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Thermal-driven analog placement considering device matching
Proceedings of the 46th Annual Design Automation Conference
Placement optimization for yield improvement of switched-capacitor analog integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the International Conference on Computer-Aided Design
Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits
Proceedings of the 50th Annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 0.00 |
One of the most important issues during the analog layout phase is to achieve accurate capacitance ratios. However, systematic and random mismatches will affect the accuracy of the capacitance ratios. A common-centroid placement is helpful to reduce the systematic mismatch, but it still needs the property of high dispersion to reduce the random mismatch [10]. To deal with this problem, we propose a simulated annealing [15] based approach to construct a common-centroid placement which exhibits the highest possible degree of dispersion. To facilitate this framework, we first propose the pair-sequence representation to represent a common-centroid placement. Then, we present three operations to perturb the representation, which can increase the degree of dispersion without breaking the common-centroid constraint in the resulting placement. Finally, to enhance the efficiency of our simulated annealing based approach, we propose three techniques to speed up our program. The experimental results show that our placements can simultaneously achieve smaller oxide-gradient-induced mismatch and larger overall correlation coefficients (i.e., higher degree of dispersion) than [10] in all test cases. Besides, our program can run much faster than [10] in larger benchmarks.