Design solutions for the interconnection parasitic effects in deep sub-micron technologies
Proceedings of the Fourth European workshop on Materials for advanced metallization
Aladin: A Layout Synthesys Tool for Analog Integrated Circuits
Analog Integrated Circuits and Signal Processing
Probabilistic congestion model considering shielding for crosstalk reduction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Two-layer bus routing for high-speed printed circuit boards
ACM Transactions on Design Automation of Electronic Systems (TODAES)
BSG-Route: a length-matching router for general topology
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Exact route matching algorithms for analog and mixed signal integrated circuits
Proceedings of the 2009 International Conference on Computer-Aided Design
Proceedings of the 48th Design Automation Conference
Estimating routing congestion using probabilistic analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Corner Stitching: A Data-Structuring Technique for VLSI Layout Tools
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Algorithmic study of single-layer bus routing for high-speed boards
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Length-Matching Routing Algorithm for High-Performance Printed Circuit Boards
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Capacitance-ratio mismatch in a switched-capacitor circuit could significantly degrade circuit performance. In the nanometer era, the parasitic effects and lengths of interconnects both have significant impacts on the capacitance ratio. This paper presents the first routing work for the problem of coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits. The router adopts a two-stage approach of topology generation followed by detailed routing to route unit capacitors such that the coupling-aware wire length ratio can match the desired capacitance ratio. Given a length ratio, in particular, the length-ratio-matching routing problem can be handled by transforming the problem into an easier classical wirelength minimization one. Experimental results show that our algorithm can solve the addressed problem with substantially smaller costs.