Proceedings of the 2009 international symposium on Physical design
An O(n log n) path-based obstacle-avoiding algorithm for rectilinear Steiner tree construction
Proceedings of the 46th Annual Design Automation Conference
Obstacle-avoiding rectilinear Steiner tree construction based on Steiner point selection
Proceedings of the 2009 International Conference on Computer-Aided Design
FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction
Proceedings of the 19th international symposium on Physical design
Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles
Proceedings of the 19th international symposium on Physical design
Reliability-Driven Power/Ground Routing for Analog ICs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees
Proceedings of the International Conference on Computer-Aided Design
An efficient algorithm for multi-layer obstacle-avoiding rectilinear Steiner tree construction
Proceedings of the 49th Annual Design Automation Conference
Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits
Proceedings of the 50th Annual Design Automation Conference
WiT: optimal wiring topology for electromigration avoidance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fast algorithm for rectilinear steiner trees with length restrictions on obstacles
Proceedings of the 2014 on International symposium on physical design
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Given a set of pins and a set of obstacles on a plane, an obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) connects these pins, possibly through some additional points (called the Steiner points), and avoids running through any obstacle to construct a tree with a minimal total wirelength. The OARSMT problem becomes more important than ever for modern nanometer IC designs which need to consider numerous routing obstacles incurred from power networks, prerouted nets, IP blocks, feature patterns for manufacturability improvement, antenna jumpers for reliability enhancement, etc. Consequently, the OARSMT problem has received dramatically increasing attention recently. Nevertheless, considering obstacles significantly increases the problem complexity, and thus, most previous works suffer from either poor quality or expensive running time. Based on the obstacle-avoiding spanning graph, this paper presents an efficient algorithm with some theoretical optimality guarantees for the OARSMT construction. Unlike previous heuristics, our algorithm guarantees to find an optimal OARSMT for any two-pin net and many higher pin nets. Extensive experiments show that our algorithm results in significantly shorter wirelengths than all state-of-the-art works.