DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
On the completeness of a generalized matching problem
STOC '78 Proceedings of the tenth annual ACM symposium on Theory of computing
Analyzing timing uncertainty in mesh-based clock architectures
Proceedings of the conference on Design, automation and test in Europe: Proceedings
MeshWorks: an efficient framework for planning, synthesis and optimization of clock mesh networks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Ispd2009 clock network synthesis contest
Proceedings of the 2009 international symposium on Physical design
Accurate clock mesh sizing via sequential quadraticprogramming
Proceedings of the 19th international symposium on Physical design
ISPD 2010 high performance clock network synthesis contest: benchmark suite and results
Proceedings of the 19th international symposium on Physical design
Combinatorial algorithms for fast clock mesh optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast timing-model independent buffered clock-tree synthesis
Proceedings of the 47th Design Automation Conference
Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cross link insertion for improving tolerance to variations in clock network synthesis
Proceedings of the 2011 international symposium on Physical design
Synthesis of low power clock trees for handling power-supply variations
Proceedings of the 2011 international symposium on Physical design
Algorithmic tuning of clock trees and derived non-tree structures
Proceedings of the International Conference on Computer-Aided Design
Multilevel tree fusion for robust clock networks
Proceedings of the International Conference on Computer-Aided Design
On construction low power and robust clock tree via slew budgeting
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
The synthesis of complex arithmetic computation on stochastic bit streams using sequential logic
Proceedings of the International Conference on Computer-Aided Design
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Local merges for effective redundancy in clock networks
Proceedings of the 2013 ACM international symposium on International symposium on physical design
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For high-performance chip designs, a clock network with high tolerance towards process-variation is essential for chip synchronization. Clock mesh structure are widely used in these designs because of its resistant to variations. However, traditional mesh structures suffer from several drawbacks such as difficulty in timing estimation, inability to handle obstacles, and high power consumption. This paper proposes a new obstacle-avoiding clock mesh synthesis method which applies a two-stage approach of mesh construction followed by driving-tree synthesis. The method achieves very low skew through structural optimization, thus eliminating the need of direct timing estimation and/or SPICE simulation during clock network synthesis. In addition, our approach handles obstacles with the structural consideration, and reduces power consumption by removing non-critical mesh components and optimizing the driving-tree structure. Based on the benchmarks of the ISPD'10 Clock Network Synthesis Contest, the top contest performers result in 1.32X skew over our approach by using mesh structure, and more than 2.0X skew over our approach by using tree structure. Our approach runs 8326X/11421X faster than teams that used simulation, and 67X/90X times faster than teams that did not use simulation.