Synthesis of low power clock trees for handling power-supply variations
Proceedings of the 2011 international symposium on Physical design
Obstacle-aware clock-tree shaping during placement
Proceedings of the 2011 international symposium on Physical design
Proceedings of the 2011 international symposium on Physical design
The future of clock network synthesis
Proceedings of the International Conference on Computer-Aided Design
Multilevel tree fusion for robust clock networks
Proceedings of the International Conference on Computer-Aided Design
Low-power clock trees for CPUs
Proceedings of the International Conference on Computer-Aided Design
High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees
Proceedings of the International Conference on Computer-Aided Design
Local clock skew minimization using blockage-aware mixed tree-mesh clock network
Proceedings of the International Conference on Computer-Aided Design
On construction low power and robust clock tree via slew budgeting
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
High-performance clock mesh optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Library-aware resonant clock synthesis (LARCS)
Proceedings of the 49th Annual Design Automation Conference
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
HEX: scaling honeycombs is easier than scaling clock trees
Proceedings of the twenty-fifth annual ACM symposium on Parallelism in algorithms and architectures
Fast power- and slew-aware gated clock tree synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Clock power minimization using structured latch templates and decision tree induction
Proceedings of the International Conference on Computer-Aided Design
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In the talk, the details of ISPD 2010 high performance clock network synthesis contest will be introduced. Compared to first clock network synthesis contest in 2009, the rules have been revised to better reflect the real problems from the industry. Instead of clock latency range upon two simulations with different supply voltage settings, the total clock power (modeled by capacitance) is set to be the major judging criteria. However, a valid clock distribution network solution must have local clock skew under a preset limit. Only local clock skew constraints will be enforced because (1) early mode timing violations are often limited in local regions, and (2) local timing violations often directly lead to congestion problems which are very hard to fix. Moreover, delay variation will be formulated in the contest and simplified Monte Carlo simulation will be used to evaluate valid solutions. More importantly, a new set of benchmarks will be announced and used to decide the winner of the contest. These test-cases are all directly derived from real industrial microprocessor and high-performance ASIC designs and they have over 1000 clock sinks. More than ten academic clock synthesis tools have participated in the contest and the final results will be announced during this talk.