Clock routing for high-performance ICs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-performance clock routing based on recursive geometric matching
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Hybrid structured clock network construction
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Reducing clock skew variability via cross links
Proceedings of the 41st annual Design Automation Conference
A multiple level network approach for clock skew minimization with process variations
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A sliding window scheme for accurate clock mesh analysis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Combinatorial algorithms for fast clock mesh optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Generation of optimal obstacle-avoiding rectilinear Steiner minimum tree
Proceedings of the 2009 International Conference on Computer-Aided Design
ISPD 2010 high performance clock network synthesis contest: benchmark suite and results
Proceedings of the 19th international symposium on Physical design
Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Planar-DME: a single-layer zero-skew clock tree router
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cross link insertion for improving tolerance to variations in clock network synthesis
Proceedings of the 2011 international symposium on Physical design
Synthesis of low power clock trees for handling power-supply variations
Proceedings of the 2011 international symposium on Physical design
The future of clock network synthesis
Proceedings of the International Conference on Computer-Aided Design
Algorithmic tuning of clock trees and derived non-tree structures
Proceedings of the International Conference on Computer-Aided Design
Multilevel tree fusion for robust clock networks
Proceedings of the International Conference on Computer-Aided Design
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Local merges for effective redundancy in clock networks
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Clock power minimization using structured latch templates and decision tree induction
Proceedings of the International Conference on Computer-Aided Design
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Clock network construction is one key problem in high performance VLSI design. Reducing the clock skew variation is one of the most important objectives during clock network synthesis. Local clock skew (LCS) is the clock skew between any two sinks with distance less than or equal to a given threshold. It is defined in the ISPD 2010 High Performance Clock Network Synthesis Contest [1], and it is a novel criterion that captures process variation effects on a clock network. In this paper, we propose a hybrid method that creates a mesh upon a tree topology. Total wire and buffer capacitance is minimized under the LCS and slew constraints. In our method, a clock mesh will be built first according to the positions and capacitance of the sinks. A top-level tree is then built to drive the mesh. A blockage-aware routing method is used during the tree construction. Experimental results show our efficiency and the solution generated by our approach can satisfy the LCS constraint of all the benchmarks in the contest [1], with a fair capacitance usage.