IEEE Transactions on Computers
Reliable non-zero skew clock trees using wire width optimization
DAC '93 Proceedings of the 30th international Design Automation Conference
Process-variation-tolerant clock skew minimization
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Sizing of clock distribution networks for high performance CPU chips
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Circuit optimization via adjoint Lagrangians
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
High speed CMOS design styles
Multi-GHz interconnect effects in microprocessors
Proceedings of the 2001 international symposium on Physical design
Computer-Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques
Computer-Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques
Fast analysis and optimization of power/ground networks
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Process variation aware clock tree routing
Proceedings of the 2003 international symposium on Physical design
Reducing clock skew variability via cross links
Proceedings of the 41st annual Design Automation Conference
A multiple level network approach for clock skew minimization with process variations
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Improved algorithms for link-based non-tree clock networks for skew variability reduction
Proceedings of the 2005 international symposium on Physical design
Analysis of buffered hybrid structured clock networks
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Process variation robust clock tree routing
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Clock Distribution Architectures: A Comparative Study
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Statistical based link insertion for robust clock network design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
An efficent clustering algorithm for low power clock tree synthesis
Proceedings of the 2007 international symposium on Physical design
Combinatorial algorithms for fast clock mesh optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Concurrent wire spreading, widening, and filling
Proceedings of the 44th annual Design Automation Conference
Discrete buffer and wire sizing for link-based non-tree clock networks
Proceedings of the 2008 international symposium on Physical design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Combinatorial algorithms for fast clock mesh optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Clock tree synthesis under aggressive buffer insertion
Proceedings of the 47th Design Automation Conference
Clock skew optimization considering complicated power modes
Proceedings of the Conference on Design, Automation and Test in Europe
Discrete buffer and wire sizing for link-based non-tree clock networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Meshworks: a comprehensive framework for optimized clock mesh network synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Local clock skew minimization using blockage-aware mixed tree-mesh clock network
Proceedings of the International Conference on Computer-Aided Design
Fast timing analysis of clock networks considering environmental uncertainty
Integration, the VLSI Journal
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Timing-driven variation-aware synthesis of hybrid mesh/tree clock distribution networks
Integration, the VLSI Journal
| Hi-index | 0.00 |
This paper hierarchically constructs a hybrid mesh/tree clock network structure consisting of overlying zero-skew clock meshes, with underlying zero-skew clock trees originating from the mesh nodes. We propose a mesh construction procedure, which guarantees zero skew under the Elmore delay model, using a simple and efficient linear programming formulation. Buffers are inserted to reduce the transition time (or rise time). As a post-processing step, wire width optimization under an accurate higher-order delay metric is performed to further minimize the transition time and propagation delay/skew. Experimental results show that the hybrid mesh/tree construction scheme can provide smaller propagation delay and transition time than a comparable clock tree.