Dealing with inductance in high-speed chip design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Full-wave PEEC time-domain method for the modeling of on-chip interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hybrid structured clock network construction
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Process variation aware clock tree routing
Proceedings of the 2003 international symposium on Physical design
Efficient Model Update for General Link-Insertion Networks
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
An efficent clustering algorithm for low power clock tree synthesis
Proceedings of the 2007 international symposium on Physical design
A novel scheme to reduce short-circuit power in mesh-based clock architectures
Proceedings of the 21st annual symposium on Integrated circuits and system design
Proceedings of the 2009 international symposium on Physical design
Routing with constraints for post-grid clock distribution in microprocessors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis of high-performance clock networks with RLC and transmission line effects
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
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High frequency on-chip interconnect examples are accurately analyzed using full-wave PEEC (Partial Element Equivalent Circuit) analysis. All wire currents and voltages (or delays) are visualized using 3D animations to aid intuitive understanding of new, high frequency interconnect effects.