Figures of merit to characterize the importance of on-chip inductance
DAC '98 Proceedings of the 35th annual Design Automation Conference
Dealing with inductance in high-speed chip design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Multi-GHz interconnect effects in microprocessors
Proceedings of the 2001 international symposium on Physical design
Exploiting the on-chip inductance in high-speed clock distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Combinatorial algorithms for fast clock mesh optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Design methodology for global resonant H-tree clock distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MeshWorks: an efficient framework for planning, synthesis and optimization of clock mesh networks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Ispd2009 clock network synthesis contest
Proceedings of the 2009 international symposium on Physical design
Non-uniform clock mesh optimization with linear programming buffer insertion
Proceedings of the 47th Design Automation Conference
Minimal buffer insertion in clock trees with skew and slew rate constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An RLC interconnect model based on fourier analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Clock tree optimization for electromagnetic compatibility (EMC)
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Interconnect has come to be a dominant factor in on-chip signal propagation, skew and jitter. As frequencies increase, more accurate modeling of the wires is necessary in order to properly estimate clock propagation. However, most wire models for clock network synthesis are based on Elmore delay, a simple first-order RC model. In this work, we analyze the discrepancies between RC, RLC and transmission line models on both skew and jitter of clock trees and grids. From our experiments, the difference in skew can be as great as 45% of the clock period for transmission lines and 7.5% for the RLC model. We argue that a deeper investigation into accurately modeling long interconnect should become a higher priority in clock network synthesis