Power optimal buffered clock tree design
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Clock skew optimization for peak current reduction
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Buffer insertion for clock delay and skew minimization
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Clock buffer polarity assignment for power noise reduction
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Analysis of high-performance clock networks with RLC and transmission line effects
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Spectral analysis of the on-chip waveforms to generate guidelines for EMC-aware design
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Minimal buffer insertion in clock trees with skew and slew rate constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Minimum buffered routing with bounded capacitive load for slew rate and reliability control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the skew-bounded minimum-buffer routing tree problem
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A simple metric for slew rate of RC circuits based on two circuit moments
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Decoupling-Capacitor Planning and Sizing for Noise and Leakage Reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Clock distribution techniques for Low-EMI design
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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Electromagnetic Interference (EMI) generated by electronic systems is increasing with operating frequency and shrinking process technologies. The clock distribution network is one of the major causes of on-chip EMI. In this paper, we discuss the EMI problem in clock tree design. Spectrum analysis shows that slew rate of clock signal is the main parameter determining the high-frequency spectral content distribution. This is the first work to consider maximum and minimum buffer slew rates in clock tree synthesis to reduce EMI. In this paper, we propose a dynamic programming algorithm to optimize the clock tree considering both traditional metrics and Electromagnetic Compatibility (EMC). Our experimental results show that slew can be controlled in a feasible range and high-frequency spectrum contents can be reduced without sacrificing the traditional metrics such as power and skew. With the efficient optimization and pruning method, the biggest benchmark is able to complete in four minutes.