Recent directions in netlist partitioning: a survey
Integration, the VLSI Journal
Clock skew optimization for ground bounce control
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Analysis and Optimization of Power Grids
IEEE Design & Test
Buffer delay change in the presence of power and ground noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Minimizing peak current via opposite-phase clock tree
Proceedings of the 42nd annual Design Automation Conference
Practical techniques to reduce skew and its variations in buffered clock networks
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Clock skew verification in the presence of IR-drop in the power distribution network
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
General skew constrained clock network sizing based on sequential linear programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Skew aware polarity assignment in clock tree
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Skew-aware polarity assignment in clock tree
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization
Proceedings of the 46th Annual Design Automation Conference
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Clock tree embedding for 3D ICs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Clock tree optimization for electromagnetic compatibility (EMC)
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Clock buffer polarity assignment with skew tuning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
WaveMin: a fine-grained clock buffer polarity assignment combined with buffer sizing
Proceedings of the 48th Design Automation Conference
Clock repeater characterization for jitter-aware clock tree synthesis
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A reconfigurable clock polarity assignment flow for clock gated designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polarities (opposite switchings) to clock buffers in an existing buffered clock tree. Three assignment algorithms are proposed: (1) partitioning, (2) 2-coloring on minimum spanning tree and (3) recursive min-matching. A post-processing of clock buffer sizing is performed to achieve desired clock skew. SPICE based experimental results indicate that our techniques could reduce the average peak current and average delay variations by 44% and 54% respectively.