A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
Buffer insertion and sizing under process variations for low power clock distribution
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A novel VLSI layout fabric for deep sub-micron applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Statistical skew modeling for general clock distribution networks in presence of process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Buffered Clock Tree for High Quality IC Design
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Reducing clock skew variability via cross links
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Improved algorithms for link-based non-tree clock networks for skew variability reduction
Proceedings of the 2005 international symposium on Physical design
A yield improvement methodology using pre- and post-silicon statistical clock scheduling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Variation tolerant buffered clock network synthesis with cross links
Proceedings of the 2006 international symposium on Physical design
Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
DiCER: distributed and cost-effective redundancy for variation tolerance
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Clock buffer polarity assignment for power noise reduction
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Skew aware polarity assignment in clock tree
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Discrete buffer and wire sizing for link-based non-tree clock networks
Proceedings of the 2008 international symposium on Physical design
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Utilizing redundancy for timing critical interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Skew-aware polarity assignment in clock tree
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2009 international symposium on Physical design
Power efficient tree-based crosslinks for skew reduction
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Routing with constraints for post-grid clock distribution in microprocessors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
On-chip em-sensitive interconnect structures
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Combinatorial algorithms for fast clock mesh optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Non-uniform clock mesh optimization with linear programming buffer insertion
Proceedings of the 47th Design Automation Conference
Clock tree synthesis under aggressive buffer insertion
Proceedings of the 47th Design Automation Conference
Discrete buffer and wire sizing for link-based non-tree clock networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cross link insertion for improving tolerance to variations in clock network synthesis
Proceedings of the 2011 international symposium on Physical design
Clock buffer polarity assignment for power noise reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multilevel tree fusion for robust clock networks
Proceedings of the International Conference on Computer-Aided Design
Crosslink insertion for variation-driven clock network construction
Proceedings of the great lakes symposium on VLSI
High-performance clock mesh optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Local merges for effective redundancy in clock networks
Proceedings of the 2013 ACM international symposium on International symposium on physical design
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Clock skew is becoming increasingly difficult to control due to variations. Link based non-tree clock distribution is a cost-effective technique for reducing clock skew variations. However, previous works based on this technique were limited to unbuffered clock networks and neglected spatial correlations in the experimental validation. In this work, we overcome these shortcomings and make the link based non-tree approach feasible for realistic designs. The short circuit risk and multi-driver delay issues in buffered non-tree clock networks are investigated. Our approach is validated with SPICE based Monte Carlo simulations, considering spatial correlations among variations. The experimental results show that our approach can reduce the maximal skew by 47%, improve the skew yield from 15% to 73% on average with a decrease on the total wire and buffer capacitance.