IEEE Transactions on Computers
An advanced diagnostic method for delay faults in combinational faulty circuits
Journal of Electronic Testing: Theory and Applications
Optimal clock skew scheduling tolerant to process variations
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Itanium processor clock design
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Cycle time and slack optimization for VLSI-chips
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Clock skew scheduling for improved reliability via quadratic programming
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Smoothed analysis of algorithms: why the simplex algorithm usually takes polynomial time
STOC '01 Proceedings of the thirty-third annual ACM symposium on Theory of computing
Statistical clock skew modeling with data delay variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Proceedings of the 39th annual Design Automation Conference
Delay Testing for Non-Robust Untestable Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A 1.5GHz third generation itanium® 2 processor
Proceedings of the 40th annual Design Automation Conference
A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Clock Scheduling and Clocktree Construction for High Performance ASICS
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
An implicit path-delay fault diagnosis methodology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Process-induced skew reduction in nominal zero-skew clock trees
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Practical techniques to reduce skew and its variations in buffered clock networks
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Dynamic thermal clock skew compensation using tunable delay buffers
Proceedings of the 2006 international symposium on Low power electronics and design
Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation
Proceedings of the 2007 international symposium on Physical design
Integration, the VLSI Journal
Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special edition on the 15th international symposium on FPGAs
Proceedings of the 45th annual Design Automation Conference
Dynamic thermal clock skew compensation using tunable delay buffers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Process variation mitigation via post silicon clock tuning
Proceedings of the 19th ACM Great Lakes symposium on VLSI
A novel resource sharing model and high-level synthesis for delay variability-tolerant datapaths
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Clock skew reduction by self-compensating manufacturing variability with on-chip sensors
Proceedings of the 20th symposium on Great lakes symposium on VLSI
A study on placement of post silicon clock tuning buffers for mitigating impact of process variation
Proceedings of the Conference on Design, Automation and Test in Europe
Clock skew minimization in multi-voltage mode designs using adjustable delay buffers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Ordered coloring-based resource binding for datapaths with improved skew-adjustability
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Fast statistical timing analysis for circuits with post-silicon tunable clock buffers
Proceedings of the International Conference on Computer-Aided Design
In-system and on-the-fly clock tuning mechanism to combat lifetime performance degradation
Proceedings of the International Conference on Computer-Aided Design
Online clock skew tuning for timing speculation
Proceedings of the International Conference on Computer-Aided Design
Useful-skew clock optimization for multi-power mode designs
Proceedings of the International Conference on Computer-Aided Design
A dynamic jitter model to evaluate uncertainty trends with technology scaling
Integration, the VLSI Journal
Dynamic management of thermally-induced clock skew: an implementation perspective
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A statistical approach to the timing-yield optimization of pipeline circuits
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
InTimeFix: a low-cost and scalable technique for in-situ timing error masking in logic circuits
Proceedings of the 50th Annual Design Automation Conference
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In deep sub-micron technologies, process variations can cause significant path delay and clock skew uncertainties thereby lead to timing failure and yield loss. In this paper, we propose a comprehensive clock scheduling methodology that improves timing and yield through both pre-silicon clock scheduling and post-silicon clock tuning. First, an optimal clock scheduling algorithm has been developed to allocate the slack for each path according to its timing uncertainty. To balance the skew that can be caused by process variations, programmable delay elements are inserted at the clock inputs of a small set of flip-flops on the timing critical paths. A delay-fault testing scheme combined with linear programming is used to identify and eliminate timing violations in the manufactured chips. Experimental results show that our methodology achieves substantial yield improvement over a traditional clock scheduling algorithm in many of the ISCAS89 benchmark circuits, and obtain an average yield improvement of 13.6%.