InTimeFix: a low-cost and scalable technique for in-situ timing error masking in logic circuits

Authors:
Feng Yuan;Qiang Xu
Affiliations:
The Chinese University of Hong Kong, Shatin, N.T., Hong Kong;The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
Venue:
Proceedings of the 50th Annual Design Automation Conference
Year:
2013

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Abstract

With technology scaling, integrated circuits (ICs) suffer from increasing process, voltage, and temperature (PVT) variations and adverse aging effects. In most cases, these reliability threats manifest themselves as timing errors on critical speed-paths of the circuit, if a large design guard band is not reserved. This work presents a novel in-situ timing error masking technique, namely InTimeFix, by introducing fine-grained redundant approximation circuit into the design to provide more timing slack for speed-paths. The synthesis of the redundant circuit relies on simple structural analysis of the original circuit, which is easily scalable to large IC designs. Experimental results show that InTimeFix significantly increases circuit timing slack with low area/power cost.