ForTER: a forward error correction scheme for timing error resilience

Authors:
Jie Zhang;Feng Yuan;Rong Ye;Qiang Xu
Affiliations:
The Chinese University of Hong Kong, Shatin, N.T., Hong Kong;The Chinese University of Hong Kong, Shatin, N.T., Hong Kong;The Chinese University of Hong Kong, Shatin, N.T., Hong Kong;The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
Venue:
Proceedings of the International Conference on Computer-Aided Design
Year:
2013

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Abstract

With technology scaling, integrated circuits suffer from increasingly severe static and dynamic variations, which often manifest themselves as infrequent timing errors on circuit speed paths, if a large timing guard-band is not reserved. This paper presents a new forward timing error correction scheme, namely ForTER, which predicts whether the occurrence of timing errors would propagate to the next level of sequential elements and corrects them without necessarily borrowing timing slack. The proposed technique can be combined with other timing error resilient circuit design techniques to further improve circuit performance, as demonstrated in our experimental results with various benchmark circuits.