On logic synthesis for timing speculation

Authors:
Yuxi Liu;Rong Ye;Feng Yuan;Rakesh Kumar;Qiang Xu
Affiliations:
The Chinese University of Hong Kong, Shatin, N.T., Hong Kong;The Chinese University of Hong Kong, Shatin, N.T., Hong Kong;The Chinese University of Hong Kong, Shatin, N.T., Hong Kong;University of Illinois at Urbana-Champaign;The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
Venue:
Proceedings of the International Conference on Computer-Aided Design
Year:
2012

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Abstract

By allowing the occurrence of infrequent timing errors and correcting them with rollback mechanisms, the so-called timing speculation (TS) technique can significantly improve circuit energy-efficiency and hence has become one of the most promising solutions to mitigate the ever-increasing variation effects in nanometer technologies. As timing error recovery incurs non-trivial performance/energy overhead, it is important to reshape the delay distribution of critical paths in timing-speculated circuits to minimize their timing error rates. Most existing TS optimization techniques achieve this objective with post-synthesis techniques such as gate sizing or body biasing. In this work, we propose to conduct logic synthesis for timing-speculated circuits from the ground up. Being able to manipulate circuit structures during logic optimization, the proposed solution is able to dramatically reduce circuit timing error rates and hence improve its throughput, as demonstrated with experimental results on various benchmark circuits.